14-bit 310-Msps dual ADC family enables linearization of 60-MHz transmit bandwidth using DPD
Digital predistortion is a closed-loop feedback system that samples the distortion bandwidth at the output of the base station transmitter and adjusts the input signal to cancel the power amplifier’s intermodulation distortion products. This enables the transmitter to operate at its highest efficiency, 1 dB compression point, where the power amplifier (PA) response is nonlinear.
Due to prior limitations in the performance of available ADCs, transmit bandwidths were limited to 20-40 MHz, depending on whether an IF sampling or I/Q sampling DPD architecture was implemented. To linearize a transmit bandwidth of 20 MHz, the feedback loop for the linearization algorithm must acquire fifth order intermodulation products out to 100 MHz (five times the transmit bandwidth), requiring a 12-bit ADC with a minimum sample rate of 200 Msps for IF sampling, or 100 Msps for I/Q sampling.
Due to increasing data demands from mobile users, next-generation base stations are being architected to achieve much higher transmit bandwidths of up to 60 MHz. To linearize a 60 MHz transmit bandwidth requires an ADC with a minimum resolution of 14-bits and an I/Q sampling architecture with a minimum sample rate of 300 Msps. In addition, the closed loop DPD algorithm requires short latency in the feedback path to achieve better efficiency in the PA.
The LTC2158-14 is the first dual, 310 Msps ADC on the market to enable linearization of transmission bandwidths up to 60 MHz using I/Q sampling, and offers a short pipeline latency of just 5 clock cycles for fast adaptation. The single version, LTC2153-14, is ideal for IF sampling architectures with transmit bandwidths of up to 30 MHz.
Operating from a single 1.8 V supply, the dual LTC2158-14 consumes 362 mW/channel at 310 Msps and offers signal to noise ratio (SNR) performance of 68.8 dB and SFDR of 88 dB at baseband with an easy-to-drive 1.32 Vp-p input range. The LTC2158 and LTC2153 are part of a pin-compatible family of 170 Msps to 310 Msps dual and single ADCs, offered in 14-bit and 12-bit resolutions. Analog full power bandwidth of 1.25 GHz and ultralow jitter of 0.15 psRMS enables undersampling of IF frequencies with excellent noise performance. The ADCs offer double data rate (DDR) LVDS digital outputs as well as programmable LVDS output current and optional 100 ohm termination.
Available in compact 9 mm x 9 mm (dual) and 6 mm x 6 mm (single) QFN packages, the ADCs may be ordered in commercial or industrial temperature grades. Demonstration boards and samples are immediately available. The 14-bit dual 310Msps LTC2158-14 is priced at $168.30 each in 1,000-piece quantities.
For further information: www.linear.com/hsadc.
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