14-bit, 500 MSPS / 1 GSPS JESD204B, analogue/digital converter

14-bit, 500 MSPS / 1 GSPS JESD204B, analogue/digital converter

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By eeNews Europe

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations and the device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use.

The analogue input and clock signals are differential inputs. The ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. The twin integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks support multiband receivers.

In addition to the DDC blocks, the AD9690 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an over-range condition at the ADC input.

Users can configure the Subclass 1 JESD204B-based high speed serialised output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronisation is supported through the SYSREF± and SYNCINB± input pins.

The AD9690 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8V to 3.3V capable 3-wire SPI.

The AD9690 comes in a Pb-free, 64-lead LFCSP and is specified over the -40°C to +85°C industrial temperature range. Use it, ADI suggests, in Multiband, multimode digital receivers for 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE; General-purpose software radios; Ultrawideband satellite receivers; Instrumentation; Radars; Signals intelligence (SIGINT); DOCSIS 3.0 CMTS upstream receive paths; or in HFC digital reverse path receivers.

Analog Devices;

next page; key specifications

JESD204B (Subclass 1) coded serial digital outputs

1.5W total power at 500 MSPS (default settings)

SFDR = 85 dBFS at 340 MHz,

80 dBFS at 1 GHz

SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 61.4 dBFS at 1 GHz

ENOB = 10.8 bits at 10 MHz

DNL = ±0.5 LSB

INL = ±2.5 LSB

Noise density = -154 dBFS/Hz at 1 GSPS

1.25 V, 2.5 V, and 3.3 V dc supply operation

No missing codes

Internal ADC voltage reference

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