1588 Ethernet designs aided by ultralow jitter network synchronisers
These network synchronizers use Microsemi’s IEEE 1588 software and are footprint compatible with the company’s recently released ZL30621, ZL30622 and ZL30623 Synchronous Ethernet (SyncE) devices, providing a migration path from G.8262 SyncE compliance to IEEE 1588 compliance.
ZL30721, ZL30722 and ZL30723 each offer a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol (PTP) stack, synchronisation algorithm and Microsemi’s system synchroniser clock generation hardware. Jitter performance is 0.25 psec root mean square (rms) and the parts have integrated EEPROM for self-configuration at start-up. The single-channel ZL30722 device comes in a 5 x 5 mm package. Combined, these features enable space-constrained, high volume IEEE 1588 applications.
These are, the company says, its smallest and lowest jitter devices to date; use them in small cell routers and switches, broadband access, carrier Ethernet equipment and wireless equipment such as base stations and backhaul equipment, as well as smart grids and synchrophasors. Microsemi’s protocol engine and time synchronisation algorithm runs on a variety of host processor architectures and is combined with an accurate timestamping unit, such as a Microsemi 1588-capable PHY or switch, and one of the new system synchronisers to provide the complete IEEE 1588 implementation. The ZL30721 and ZL30722 have three input references and generate up to three differential, or six single-ended output clocks, while the ZL30723 has six input references and generates up to six differential or 12 single-ended output clocks.
– Packet network frequency and phase synchronisation; Frequency accuracy for GSM, WCDMA-FDD, LTE-FDD base stations and small cells; Frequency performance for ITU-T G.823 and G.824 synchronisation interface, G.8261 PNT, PEC and CES interfaces; Phase synchronisation performance for WCDMA-TDD, TD-SCDMA, CDMA2000, LTE-TDD and LTE-A applications; Client holdover and reference switching between multiple servers; Support for new ITU-T packet clock, G.8263 PEC, G.8273.2 T-BC, T-TSC
– IEEE 1588 protocol engine; IEEE 1588-2008 Annex J.3 (delay request response) and Annex J.4 (peer-to-peer) default profiles; ITU-T G.8265.1 PTP telecom profile for frequency synchronisation; ITU-T G.8275.1 PTP telecom profile for phase/time synchronisation with full timing support from the network; IEEE C37.238-2011 power profile requirements with grandmaster, boundary clock and slave only ordinary clock functionality; Low-bandwidth digital phase locked loop (DPLL) per channel; Programmable bandwidth from 0.1Hz to 500Hz; Hitless reference switching; High-resolution holdover averaging; Numerically controlled oscillator mode
– Low-jitter fractional-N APLL and three outputs per channel