16/32-Mbit low-power SRAMs boost soft error immunity by 500x
Two series of Advanced LP SRAM, the leading type of low-power-consumption SRAM, are designed to provide enhanced reliability and longer backup battery life for applications such as factory automation (FA), industrial equipment, and the smart grid. Fabricated using a 110-nm process, the RMLV1616A Series of 16-Mb devices and the RMWV3216A Series of 32 Mb devices use an innovative memory cell technology that improves reliability and contributes to longer battery operation.
Demands for highly secure and reliable user systems are driving increased demand for highly reliable SRAM, to store information such as system programs and financial transaction data. The prevention of soft errors caused by alpha particles and cosmic neutrons is a significant issue. Typical measures to deal with this problem include embedding an error correcting code (ECC) circuit in the SRAM or user system to correct any soft errors that occur. There are limits, however, to the error correction capabilities of ECC circuits. For example, some cannot correct simultaneous errors affecting multiple bits.
Renesas’ Advanced LP SRAM devices feature proprietary technology in their memory cells that achieves soft error resistance over 500 times that of conventional Full CMOS memory cells.
In the Renesas Advanced LP SRAM structure, a stacked capacitor is added to each memory node within the memory cells. This configuration suppresses the generation of soft errors to a level that is effectively soft error free. The load transistor (P-channel) of each SRAM cell is a polysilicon thin-film transistor (TFT) that is stacked on top of the N-channel MOS transistor formed on the silicon. Only the N-channel MOS transistor is formed on the silicon substrate below. This means that no parasitic thyristors are formed in the memory area and theoretically makes latch-up impossible. Therefore, the Advanced LP SRAM is well suited to applications requiring high reliability.
The standby current of the new RMLV1616A Series and RMWV3216A Series is only 0.5 μA (typical) for 16 Mb devices and 1 μA (typical) for 32 Mb devices. These low current consumption levels are less than half the levels of comparable earlier Renesas SRAM products. The minimum power supply voltage when retaining data is 1.5V, lower than the 2.0V of comparable earlier Renesas products.
The 16 Mb RMLV1616A Series is available in three packages: 48-ball FBGA, 48-pin TSOP (I), and 52-pin μTSOP (II). The 32 Mb RMWV3216A Series is available in a 48-ball FBGA package.
Samples of the RMLV1616A Series and RMWV3216A Series will be available in September. Mass production using the 110 nm process has already begun for Advanced LP SRAM products with 4 Mbit and 8 Mbit capacities.
Full CMOS memory cells means an SRAM memory cell configuration in which a total of six P-channel MOS transistor and N-channel MOS transistor elements are formed on the same plane of the silicon substrate. The surface area is large and there is a latch-up risk. (In which an NPN or PNP structure (parasitic bipolar transistor) formed by the well, silicon substrate, P-type diffusion layer, and N-type diffusion layer of a CMOS transistor enters the on state due to overvoltage from the power supply or input pins, allowing a large current to flow between the power supply and ground.)
Stacked capacitor: Capacitors with two electrodes formed from polysilicon or metal. These capacitors are formed on the upper layer of the MOS transistors on the silicon substrate.
Renesas has published on its website the results of its evaluations of soft errors in systems employing Advanced LP SRAM. These evaluations were run for more than a year under conditions similar to the usage environment of average users, and in the end no errors were detected. See;
www.renesas.com/products/memory/low_power_sram/child/renesas_effort.jsp
Renesas; www.renesas.eu
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
