16-bit digital signal controller delivers deterministic performance in time-critical applications
Designed to deliver faster deterministic performance in time-critical control applications, the dsPIC33CK has expanded context selected registers to reduce interrupt latency and new faster instruction execution to accelerate Digital Signal Processor (DSP) routines. The dsPIC33CK single-core family complements the recently announced dsPIC33CH dual-core family based on the same core.
With 100 MIPS performance, the core of the dsPIC33CK delivers almost double the performance of previous single-core dsPIC DSCs, making it ideally suited for motor control, digital power and other applications requiring sophisticated algorithms such as automotive sensors and industrial automation. It has been designed specifically for controlling multiple sensorless, brushless motors running field-oriented control algorithms and power factor correction.
The devices include integrated functional safety features for safety-critical designs such as: RAM Built-In Self-Test (BIST) for checking RAM health and functionality; Deadman Timer for monitoring the health of application software through periodic timer interrupts within a specified timing window; Dual Watchdog Timers (WDT); Flash Error Correction Code (ECC); Brown Out Reset (BOR); Power On Reset (POR); and Fail Safe Clock Monitor (FSCM). A CAN-FD communication bus supports new automotive communication standards. The dsPIC33CK is available in eight package variants which include packages from 28 to 80 pins and as small as 5x5mm. Memory sizes range from 32 to 256 KB of Flash.
Microchip – www.microchip.com
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