16 core RISC-V chip for space designs
Cobham Advanced Electronic Solutions (CAES) is to develop a fault tolerant and radiation tolerant 16 core RISC-V processor chip for space systems.
The project is funded by the Swedish National Space Agency, backed by the European Space Agency, at the CAES Swedish Gaisler subsidiary.
The GR7xV processor will be designed into spaceborne controls and payload data management and processing systemas to enable new kinds of observational, communication, navigational and scientific missions and services. These include advanced, flexible telecommunications satellite payloads, scientific and earth-observation payloads and robotics systems such as planetary exploration rovers.
The processor will extend the CAES Gaisler Product family of LEON processors, which have been used in space applications for decades and are based on legacy 32-bit SPARC V8 ISA microprocessor cores.
Other multi-core processor and IP designs are in progress across Europe using the RISC-V open instruction set architecture (ISA).
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“ESA is proud to work with CAES on this new technology development as it will enable future missions and advance the technological standard for space processors,” said Elodie Viau, Director of Telecommunications and Integrated Applications at ESA.
“The ESA contract further advances our development of a fault- and rad-tolerant space-grade microprocessor with unprecedented performance for its class,” said Sandi Habinc, General Manager, CAES Gaisler Products. “The open RISC-V ISA has seen significant adoption in other markets, and this project is the first to develop a RISC-V-based ASIC for space applications.”
The ESA contract follows a contract awarded earlier this year by Vinnova, Sweden’s innovation agency, to extend the RISC-V processor platform to space-hardened applications for timing isolation and cybersecurity. The results of that study will be used to advance space-hardened GR7xV microprocessor development and will be shared with the industry at large.
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