16-Port 50GbE PHY transceiver targets hyperscale data centers
Purpose-built to address the I/O speed transition in hyperscale data centers from 25GbE (Gigabit Ethernet) and 100GbE to 50GbE, 200GbE and 400GbE, the chip supports 16 ports of 50GbE, 4 ports of 200GbE and 2 ports of 400GbE, utilizing 50G PAM4 signalling.
The transceivers are also the first PHY devices on the market to be fully compliant with new IEEE 802.3cd standards that define PAM4-based 50GbE port types. The port density on the 88X7120 has been specifically optimized to enable QSFP-DD (Quad Small Form Factor Pluggable – Double Density) and OSFP (Octal Small Form Factor Pluggable) port types for 50GbE, 200GbE and 400GbE deployments. The devices also provide gearboxing functionality for translating between PAM4 and NRZ port types to enable a smooth transition to the newer Ethernet speeds, while maintaining support for existing optics and ASIC I/Os. They have a fully symmetric architecture, with long reach SerDes on both system and line side interfaces, to enable system design flexibility and to support both optical and direct-attach copper interconnects. The 88X7120 is sampling to key customers today.
Marvell – www.marvell.com
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