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IBM and Samsung Electronics have proposed a vertical transistor with lower power consumption and better scaling at 2nm than horizontal nanosheet transistors.


IBM and Samsung claim the vertical transport FET (VTFET) (above) has the potential to reduce energy consumption at the same frequency of operation by 85 percent compared to a scaled FinFET.

This is based on simulations of transistors with the same footprint at a sub-45nm gate pitch. An alternative comparison is that the VTFET provides approximately twice the performance of the scaled FinFET at equivalent power due to VTFET maintaining good electrostatics and parasitics while FinFET performance is impacted by scaling constraints.

The team was able to build I/O VTFETs and functional ring oscillators using the process. The vertical current transistors do require a vertical gate connection a second parallel return connection to the interconnect which would still conventionally lie above the silicon surface. That is three vertical connections in total for source, gate and drain.

Nonetheless the expectation is that this form of transistor would scale better than FinFET and would allow more transistors to be packed into a given area. It may be possible in the future to vertically stack VTFETS to produce a vertical CMOS.

IBM recently announced a 2nm manufacturing process that would allow 50 billion transistors in approximately 1 square centimeter

Samsung is due to manufacture chips for IBM server platforms at the 5nm node following on from the 2018 announcement that Samsung would manufacture 7nm chips for IBM.


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