18bit SAR ADC slashes latency, power

Technology News |
By Nick Flaherty

Texas Instruments has developed a family of high resolution, high speed, low latency analogue to digital converters (ADCs) with a digital downconverter to simplify the interface to a microcontroller.

The aim is to simplify the digital control loop for capturing signals with 14 to 18bit resolution and latency as low as 8ns with a successive approximation register (SAR) ADC conversion architecture.

“What we are talking about with this family is nanoseconds of latency. This brings flexibility and real time tunability from the digital control loop where an analogue control loop isn’t necessarily flexible. This means one board can be programmed for different applications,” said Matthew Hann,  Product Line Director for RF Sampling and High Speed ADCs at TI.

“For example a fault detection system with a fast decision and smart shutdown control needs time accuracy, not just precision. This is leading into a system that’s precise, efficient, safe and reliable,” he said.  

“For example GaN FETs are faster than silicon FETs so the respond time out of the digital control loop was demanding the speed but the architecture is different form a pipeline – it is a SAR so that doesn’t add latency from the pipeline. By low latency variant we mean one clock cycle at 8ns,” he said.   

The ADC family is 8 devices pin to pin compatible across the single channel and dual channel variants from 14 to 18bits.The common footprint means the engineer can design one board for different resolutions says Hann. A single 65nm die is bonded out into the single channel or dual channel variants.

The low noise and lower power consumption of the SAR ADC can also reduce components in the signal path such as simpler antialiasing filter that also acts as a glitch filter to also reduce system power consumption.

The downconverter uses a 32bit resolution numerically controlled oscillator (NCO) to decimate a signal for a digital interface. “We are bringing the compute capability from the processor into the SAR ADC. The digital downconverter makes it easier to communicate the data over the digital interface, sampling a large spectrum of data and only transmit the data of interest over the interface and this can simplify the number of lines and means the design might only need a low cost controller rather than an FPGA. The Downconverter decimates x4, x8 up to 32 so can chose the decimation compared to the signal rate.”

“We are trying to push both low noise and high speed. There are devices at this sampling rate but we bring better noise performance, integrated digital features and lower performance

The ADC3683 18bit ADC samples at 65 MSample/s with a signal-to-noise ratio (SNR) of 84.2 dB and a noise spectral density of -160 dBFS/Hz while maintaining low power consumption of 94 mW per channel for applications such as portable radios.

Consuming 36mW total, the 10-MSa/s 14bit ADC3541simplifies thermal management and extends battery life in power-sensitive applications such as GPS receivers or handheld electronics. The 65MSPS, 16bit ADC3660 delivers 82 dBFS SNR, improving image resolution in sonar applications while consuming less power at 71 mW per channel.

The ADC3563, ADC3583, ADC3643, ADC3660, ADC3663, ADC3664 and ADC3683 are available now from TI in a 5-mm-by-5-mm very thin quad flat no-lead (WQFN) package. Pre-production versions of the ADC3541 are available now, only on, with volume production expected in the first quarter of 2022. Evaluation modules are available from TI for US$249.

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