The compiler supports the company’s low power, single port SRAM IP and dual port SRAM IP for 28nm FDSOI process technology. It offers capacities up to 1Mbit with word lengths up to 288 bits and supports 4, 8 and 16 Mux factors. The single port SRAM IP supports an operating voltage range of 0.6 – 1.2V and claims dynamic power savings exceeding 50% relative to those of current commercial offerings. The IP also cuts static power by up to 35% with only a modest, under 10%, area penalty.
The sureCore compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enhance and speed the design process.
"The availability of this new compiler marks a key milestone for sureCore and demonstrates that the power saving technologies we developed are now available to the SoC design community," said sureCore’s Chairman, Guillaume d’Eyssautier.
sureCore’s silicon-proven, 28nm FDSOI IP targets applications that demand long battery life with minimal operating and stand-by power performance. The IP also provides value in the networking space where power and heat dissipation are critical. The company will follow the 28nm FDSOI compiler with a 40-nm ultra-low power compiler, with an anticipated release date of March 2016, that targets the leading foundry process. The company’s product roadmap also includes the introduction of a 40 nm CMOS ultra low power SRAM in 2017. Work also continues on a 28 nm CMOS solution.
"There is still considerable innovation happening at relatively mature production nodes," said sureCore’s CEO, Paul Wells. "With the growing IoT market, mature nodes such as 40 nm are 28 nm are taking on an extended life. Their cost performance is ideal for the IoT technical and business challenges."