28nm FD-SOI and full voltage scaling break low-power limits for DSPs
Produced by ST, the device allows body-bias-voltage scaling from 0V to +2V, it decreases minimum circuit operating voltage and supports a clock frequency up to 460MHz at only less than 0.4V. The two partners presented a paper also describing 2.6GHz clocking at 1.3V as well as a demonstration kit.
The demonstrator achieves UWVR, greater energy efficiency, and unprecedented levels of efficiency in voltage and frequency using a combination of design techniques, both claim ST and Leti who developed and optimized standard cells libraries over the 0.275V-to-1.2V range. Among the optimized cells, fast pulse-triggered flip-flops are designed for variability tolerance at low voltage.
Additionally, on-chip timing-margin monitors dynamically adjust the clock frequency to a few per cent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology.
As a result, even at 0.4V, the DSP exhibits a ten-fold increase in operating frequency compared to state-of-the-art competing solutions, boast the companies.
“This demonstration DSP shows that FD-SOI is blazing the trail for better portable and battery-powered products, using more efficient semiconductor chips, all the way down to the 10nm node,” reportedly said Philippe Magarshack, Executive Vice President, Design Enablement Services at STMicroelectronics.
Visit CEA-Leti at www.leti.fr
Visit STMicroelectronics at www.st.com
Related articles:
Considerations for Bulk CMOS to FD-SOI Design Porting
Second sourcing for STMicro‘s 28nm and 20nm FD-SOI technology with Globalfoundries
FD-SOI less ‘risk’ than FinFETs, says SOI body
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