2nm forksheet structure to beat gate-all-around devices, show simulations

2nm forksheet structure to beat gate-all-around devices, show simulations

Technology News |
By eeNews Europe

TCAD simulations of the forksheet device with reduced n-to-p spacing show a 10 percent performance increase compared to nanosheet devices and a 20 percent cell area reduction compared to gate-all-around nanosheet devices. When combined with scaling boosters, the new device architecture will bring logic standard cell height down to 4.3 tracks, which combined with cell template optimization can result in more than 20 percent area reduction, the researchers say.

The forksheet device has recently been proposed by imec as a natural extension of vertically stacked lateral gate-all-around nanosheet devices. Contrary to the gate-all-around nanosheet device, in the forksheet, the nanosheets are now controlled by a tri-gate forked structure, realized by introducing a dielectric wall in between the P- and NMOS devices before gate patterning. This wall physically isolates the p-gate trench from the n-gate trench, allowing a much tighter n-to-p
spacing – a challenge that could not be answered with FinFET or nanosheet structures.

Because of this reduced n-to-p separation, the forksheet is expected to have superior area and performance scalability. For the first time, standard cell simulations confirm this excellent power-performance-area (PPA) potential of the forksheet device architecture. The device under study targets imec’s 2nm technology node, using a contacted gate pitch of 42nm and a 5T standard cell library with a metal pitch of 16nm. The proposed design includes scaling boosters such as buried power rails and wrap around contacts.

Compared to a nanosheet device, the researchers report a 10 percent speed gain (at constant power) and a 24 percent power reduction (at constant speed). The performance boost can be partly explained by a reduced miller capacitance, resulting from a smaller gate-drain overlap. Finally, the n-to-p separation reduction can be used to reduce the track height from 5T to 4.3T.

When implemented in an SRAM design, the simulations reveal a combined cell area scaling and
performance increase of 30 percent for 8nm p-n spacing.

Imec –

Related articles:

Samsung to introduce nanosheet transistors in 3nm node

A SPICE model for Gate-All-Around transistors

IEDM: Samsung makes 3nm gate-all-around CMOS

Atomic layer etching yields 2.5nm wide FinFETs


If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles