310-MSPS dual A/D converter features -156-dBFS noise floor
The AD9652 can digitize up to 155 MHz of signal bandwidth and provides an analog input bandwidth of 650 MHz. The high performance input buffer and 16-bit A/D converter core provide the high linearity and noise performance necessary to detect and isolate weak signals in the presence of large signals, blockers, and spectral clutter. This can simplify the signal chain and move more of the system control, configuration, and tuning into the software domain. Target applications for the ADC include multi-mode, multi-band, communications receivers, RADAR, and RF test equipment.
The AD9652 supports input clock frequencies up to 1.24 GHz with an integer 1-to-8 clock divider used to generate the A/D converter sample clock. A duty cycle stabilizer is provided to compensate for variations in the A/D converter clock duty cycle. The 16-bit output data (with an over-range bit) from each A/D converter is interleaved onto a single LVDS output port along with a double-data-rate clock. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.
The ADC features high dynamic range for IF sampling: SNR of 73.7 dBFS at 170 MHz (AIN of -1 dBFS) and SFDR of 85 dBFS at 170 MHz (AIN of −1 dBFS). The device has excellent noise spectral density (NSD) performance: −156.7 dBFS/Hz input noise and −157.6 dBFS/Hz for small signal, <-6 dBFS at 70 MHz.
Other features include 90-dB channel isolation/crosstalk, on-chip dithering (improves small signal linearity), and analog bandwidth of 650 MHz.
The AD9652’s dual A/D converter cores feature a multi-stage, pipelined architecture with integrated output error correction logic. A high-performance on-chip buffer and internal voltage reference is used to simplify the interface to external driving circuitry while preserving exceptional dynamic performance.
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