3D die-on-die IP for TSMC 5nm process

3D die-on-die IP for TSMC 5nm process

Technology News |
By Nick Flaherty

Taiwanese chip designer Global Unichip Corp (GUC) has launched 3D die-to-die interconnect for TSMC’s 5nm N5 and N6 process technology for AI, HPC, and networking chips.

Demand for memory in AI, HPC and networking chips is growing quickly and the SRAM to Logic ratio is also increasing. Logic gains higher density and performance when scaled to N5/N3 process nodes but SRAM scaling from the 7nm N7 process to N5 and N3 is moderate.

GUC’s GLink-3D achieved six times higher bandwidth/area density, six times lower latency and twice lower power consumption than its previous 2.5D interface (GLink-2.0) that taped out in Dec 2020.

Separating out the SRAM and logic allows the most efficient process nodes, but requires new assembly techniques in the packaging. Layers of CPU and SRAM die for cache and packet buffers dies can be assembled over and under interconnect/IO dies using TSMC’s 3DFabric packaging technology.

Such expandable SRAM and modular computing applications are enabled by GUC GLink-3D high bandwidth, low latency, low power, and point-to-multipoint interface between 3D stacked dies. This allows the CPUs, SRAMs, interconnects and I/Os such as SerDes, HBM, DDR to all be implemented in different process nodes, with different die combinations assembled to address different market segments. At boot time, assembled SRAM and CPU dies are identified, unique die IDs are distributed, available memory space and computing resources are defined and a point-to-multipoint GLink-3D interface to the stacked dies is enabled.

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TSMC’s 3DFabric SoIC platform technology allows more efficient connectivity as several 3D die stacks can be assembled using CoWoS and InFO_oS, interconnected using GLink-2.5D links and combined with HBM memories.

“GLink-3D is a new addition to a rich portfolio of best-in-class and silicon-proven HBM2E/3 PHY/Controller and GLink-2.5D IPs. CoWoS, InFO_oS, 3DIC expertise, package design, electrical and thermal simulations, DFT and production testing under one GUC roof provide our ASIC customers with quick design cycles, fast bring up  and production ramp up,” said Dr. Ken Chen, president of GUC.

“3D die stacking technology will start a revolution in the way we design HPC, AI and Network Processors. Die-to-die interface is not limited any more to the die boundary, it can be located exactly where processors need to connect to SRAM and additional CPUs. 3DFabric and GLink-3D pave way to the processors of the future, combining huge and scalable processing power with vast, high bandwidth and low latency memory, when every component is implemented using the most efficient process node.” said Igor Elkanovich, CTO of GUC.

GLink-3D supports TSMC-SoIC stacking of combination of N5 and N6 process nodes with point-to-multipoint interface allows the main die to interface with several stacked dies simultaneously and full duplex 9Tbps traffic per mm2 at 5.0 Gbps per lane. The end-to-end latency is under 2ns with low power design of less than 0.2pJ/bit from a single supply voltage of 0.75V ± 10 percent.

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