3D hierarchical extractor for post-layout verification boasts unlimited capacity
As a hierarchical extractor, H3D is suited for array-based and repetitive design structures, including memories, FPGAs, and image sensors. Based on Silicon Frontline’s patented technology, H3D’s extraction performance is sub-linear, which ensures that as design size grows extraction performance improves. By providing a hierarchical output netlist, post-layout simulation performance becomes sub-linear when using hierarchical simulators. H3D hierarchical extraction results are design dependent, but have shown performance improvements from 20-120x when compared to flat extraction, according to the EDA vendor.
Built on a Hierarchical Random Walk Algorithm, users have the ability to specify the accuracy required on a net by net or block by block basis. H3D provides unlimited capacity due to its hierarchical extraction and parallelization.
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