3D magnet stack subs for transistors

The researchers also contend that their 3D magnetic transistor-substitutes could be fabricated into any type of gate on standard complementary metal oxide semiconductor (CMOS) lines and are currently inventing magnetic logic techniques that could substitute for CMOS logic and memory functions.

The team’s first demonstration, in collaboration with Notre Dame, is a majority logic gate that could serve the same function as a logic switch using CMOS transistors. It works by stacking three nanomagnets so that opposite poles attract and like poles repel. Depending on which way they are oriented, the poles can represent 1s and 0s. One magnet sits 60 nanometers below the other two and is read out by a single output magnet. To make the whole arrangement work the materials had to be carefully selected and tested.

Scanning electron micrographs (SEM) of a 3D majority logic gate (left) showing the scale of the computing area (with dimensions less than 200 nanometers, upper right) and (lower right cross-section) the lower position of the third input magnet. (Source: I. Eichwald/TUM)

"The material, that can be used is a cobalt/platinum or a cobalt/nickel in a multilayer stack. There are two things that we make sure of: that the material must possesses perpendicular magnetic anisotropy to get a bistable magnetization state of the magnets, and that the anisotropy must be tunable by focused ion-beam irradiation. A cobalt/platinum or a cobalt/nickel multilayer stack fulfills both criteria," Professor Markus Becherer told EE Times.

"The magnets themselves are all stationary on the chip," Becherer explained. "The only thing that is moving, is the domain wall in the irradiated output magnet. This domain wall reverses the output magnet by moving through the entire output magnet. But whether a domain wall is nucleated or not in the output magnet, it is controlled by the stray field of the input magnets."

The polarity of the nanomagnets can also be switched by a network of nanowires interwoven into the substrate and passing across the nanomagnets so that their polarity can be switched at will with the help of gate magnets.

"Domain walls propagate in the nanowire in order to switch the magnetization of the whole nanowire. A domain wall gate is able to block the propagating domain wall by a gate magnet. By blocking the domain wall, the end of the nanowire remains in its previous magnetic state, which is therefore buffered. So the nanowire is split into two independent domains controlled by the domain wall gate. The end of the nanowire (the input for subsequent gates) stays in its magnetic state until the domain wall gate allows the domain walls to pass through," Becherer told EE Times.

Magnetic force micrographs (MFM) of a 3D majority logic gate showing magnetization states of three input and one output magnet. (Source: I. Eichwald/TUM)

One advantage of nanomagnetic logic is that it takes fewer components to built modules, like a full adder, by eliminating and AND and OR gates needed in classic CMOS transistor implementations.

"Usually, majority gates possess three equal input magnets acting on one single output magnet. However, the number of inputs is not limited to three, but can be extended to an arbitrary number. Thereby, the influence of the input magnets in a majority gate can be weighted by the inputs size and distance to the output. This allows us to build majority gates with weighted inputs — an analog to a technique called threshold logic which was invented in the 1970s. Threshold logic gates require several transistors, AND, OR gates in classical CMOS technology. But in nanomagnetic logic, it is on a single gate with several weighted inputs. Thus, a 1-bit full adder in nano-magnetic logic is realized by only five interacting magnets whereas in CMOS about 20 to 30 transistors are required depending on the full adder architecture," Becherer told EE Times.

Right now the nanomagnets are operating at about the 45nm node of the International Technology Roadmap of Semiconductors (ITRS), but the researchers point out that transistors are much bigger than the technology node at which they are specified, which only measures the gate length. Whereas since nanomagnet logic gates are 3D the whole gate is confined within its length.

From left, the magnetic-computing research team at TUM: Stephan Breitkreutz, Irina Eichwald, Markus Becherer. (Source: U. Benz/TUM)

"The technology node describes more or less the most critical dimension of a CMOS transistor, which is the gate length. So briefly, the length of a transistor gate is about 45nm at the 45nm node. Whereas the most critical criteria for the size nano magnetic logic is that which maintains their thermal stability. Today a single magnet itself can be downscaled to 50nm x 50nm in terms of surface area (thickness of the magnets is as small as 10nm)," Becherer told EE Times. "And, if you consider a transistor (with source, drain and contacts), it is actually bigger than the technology node itself. For a  50nm x 50nm magnet, which constitutes a transistor, the 45nm technology node would be sufficient and the circuits would still remain smaller than in the current CMOS technologies."

Stephan Breitkreutz using a self-built measuring instrument to probe the switching behavior of nanomagnetic devices. (Source: U. Benz/TUM)

The team members believe they have discovered a fork in the ITRS roadmap, where silicon transistors will continue down one track while magnetic transistor analogs will continue down a parallel track, with CMOS chips free to incorporate both technologies into their systems on chip (SoC).

Magnetic gates and bits have several advantages: they are inherently nonvolatile and radiation proof, and they consume very little energy when switching and zero power when idle. They substitute coupling magnetic fields for interconnection wires and require fewer components for common subsystems.

Funding was provided by the German Research Foundation (DFG).

— R. Colin Johnson, Advanced Technology Editor, EE Times