3D multi-layer stacking for imaging applications
Over the past decade there has been a strong push for improved electronics performance by using smaller designs; this in turn, has stimulated rapid advances in integrated technologies. Among these, 3D integration methods stand out as particularly promising
3D integration facilitates the combination of multiple functions within a tight space, enhancing performance while limit ing power consumpt ion. As a result, 3D stacked memories, chiplets, and heterogeneous integration are all gaining traction. Nevertheless, in recent years, complementary metaloxide semiconductor (CMOS) imager sensors (CIS) have clearly led the way in 3D integration. Among the emerging technologies in image sensing, a key trend is 3D multi-layer stacking. Al ready, 2-layer based imagers benefit from 3D hybrid-bonded stacking methods that make it possible to combine two separately-optimized technologies: dedicated pixel tech nolog y ( low noise, high dynamics, high QE), and advanced analog and digital CMOS (high-density, low-power). To further advance this multi-layer integration, a third layer can be added. Three-layer integration is particularly interesting because, in addition to allowing separate optimization of the individual layers, it offers additional silicon to implement new functions, place innovative partitioning solutions, or use different advanced technology nodes. Three-layer approaches thereby contribute to the pursuit of the pixel shrink race, while maintaining optical performances. They also make it possible to envisage the direct implementation of a neural network and memory, to build artificial intelligence (AI) into the sensor itself. The technologies required for this new generat ion of smart imagers based on embedded AI a re being developed by CEA-Let i within the framework of the IRT Nanoelec/Smart Imager Program that involves CEA, STMicroelectronics, Siemens EDA, Prophesee, Lynred, and Grenoble INPUGA. The program tackles all the key challenges, from innovative architectures to the design and development of silicon technologies. In particular, the combination of hybrid bonding and high-density through-silicon vias (HD TSVs) is promising for the integration of the various components of imagers. This article presents CEA-Leti’s silicon technology developments involving wafer-to-wafer hybrid bonding and HD TSVs, with recent key demonstrations of 2-layer and 3-layer integrations. These demonstrations pave the way to the next generation of smart imagers
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