4-channel, 100G networking streams on a single programmable logic device
The packet processing middleware, combined with Tabula’s new 22nm ABAX2P1 3PLD device allow processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G‐to‐100G bridge. These are enabled by Tabula’s 3D architecture, RTL compiler and leading‐edge process technology.
“With the migration from 10G to 40G and 100G, FPGA users are having a hard time delivering the kind of throughput needed by these systems,” said Rich Wawrzyniak, Senior Market Analyst: ASIC & SoC at Semico Research. “With this set of programmable solutions, Tabula is demonstrating that their 3PLD devices can support four 100G streams on a single programmable device, something not achievable on other programmable solutions.”
The high‐performance packet processing reference design suite is composed of a 12x10G‐to‐100G bridge reference design kit, implementing an aggregation function commonly used in communications systems and using the ABAX2P1 device’s high performance bus‐handling capabilities, as well as a 4 x100G switch reference design kit, targeting data center migration from 10G to 40G and 100G. A 2nd‐generation Ternary Search Engine (TSE) reference design kit is aimed at the search capabilities required for leading‐edge routers and NGFW.
The company also delivers a complete set of design examples and soft IP cores tailored for many of the most performance‐critical functions found in high‐performance packet processing equipment. Examples include a 600Gbps packet classifier, a 100Gbps 64‐bit CRC generator, and a 1.3Tbps L2 packet parser.
“The capabilities we have demonstrated are simply out of reach of even the most advanced FPGAs,” said Dennis Segers, Tabula’s Chief Executive Officer. “With this comprehensive suite of programmable solutions, we are uniquely supporting the migration from 10G to 40G and 100G that is currently underway.”
Tabula’s four core technology components include the Spacetime 3D architecture which employs time, rather than space, as a third dimension, allowing every resource on the chip to perform multiple, different functions per user
cycle – up to 12 in the current generation. Chips using Spacetime, called 3PLDs, are nevertheless presented as having three spatial dimensions with all of their resources distributed across 12 floors or folds, which dramatically reduces die size vs. FPGAs. In addition, all components in a 3PLD – logic, RAM, multiply/accumulate blocks, and interconnect – operate in concert at up to 2
GHz, eliminating the performance bottlenecks that exist in FPGAs.
The Stylus compiler integrates cutting‐edge technologies, such as sequential timing, router aware placement, and automatic co‐optimization of performance and density to offer simpler, more intuitive RTL design and a faster timing closure loop. The ABAX2P series of devices are built on Intel’s advanced 22nm Tri‐Gate process for high speed at low operating voltage for reduced power. Production scalability to meet the highest volume demands is supported via this key alliance.
The ABAX2P1 3PLD chip is a 12‐fold Spacetime device that includes a programmable fabric supporting 2 GHz throughput through every component of the chip – logic, RAM, MAC blocks, and interconnect, with 23.3 Mbytes of 12‐ and 24‐port on‐chip memory delivering 13.8TB/s of throughput – enough to support multiple 100G streams
Multiple, built‐in, hard, DDR3 controllers operating at 2.133 GT/s, the maximum DDR3 rate, provide the bandwidth necessary to support external packet buffering or storage of search tables for multiple 100G streams while multiple 100G Ethernet MACs to ensure easy timing closure and low resource utilization of these ultra‐high‐performance standard blocks.
The initial set of high‐performance packet processing solutions is incorporated in Stylus and is available now. Additional suite offerings are scheduled to be released on a monthly basis. Engineering samples of ABAX2P1 will be available in Q3.
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