MENU

$400m RISC-V design centre for Barcelona

Business news |
By Nick Flaherty


Intel has teamed up with the Barcelona Supercomputing Centre to establish a lab to develop the next generation of zettascale supercomputers based around the RISC-V instruction set architecture.

The $400m funding over the next ten years at the Centro Nacional de Supercomputación (BSC-CNS) will come from Intel and the Spanish Government through the PERTE Chip project as part of the Recovery, Transformation and Resilience Plan. The joint laboratory is expected to create 300 jobs and will be an innovation hub that will attract new international investment. It will also aid the creation of a robust system for the future of supercomputing in Europe.

The laboratory will be located in Campus Nord at the Polytechnic University of Catalonia, where BSC-CNS’s facilities are also based.

The Barcelona centre is already a key partner in the development of RISC-V chips for European supercomputers, including a 22nm RISC-V chip accelerator for the European Processor Initiative.

Zettascale supercomputers will be 1000 times faster than today’s most powerful supercomputers that are just reaching the exascale performance levels. Intel has made a major push into developing RISC-V designs internally and for partners. The ability to add custom extensions for specific applications helps to boost performance at lower power consumption.  

The chips will also be used for autonomous cars and for artificial intelligence.

“We are very pleased that Intel has chosen BSC to create a research lab together that will be a world leader in chip design. One of the objectives will be for future European supercomputers, such as MareNostrum 6 within 5 years, and many others worldwide, to incorporate technology developed in this lab. In addition, the lab will help create a hub for new companies and jobs,” said Mateo Valero, director of BSC-CNS.

”High-performance computing is the key to solving the world’s most challenging problems and we at Intel have an ambitious goal to sprint to zettascale era for HPC. Barcelona Supercomputing Centre shares our vision for this goal, with equal emphasis on sustainability and an open approach. We are excited to partner with them to embark on this journey,” said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel.

This follows the establishment of a European design centre in Malaga for Vodafone that will also work on RISC-V chip designs. 

Other RISC-V articles

Other articles on eeNews Europe

 


Share:

Linked Articles
10s