48V fully integrated GaN DC-DC converter
Researchers at the University of Texas at Dallas have developed a monolithic asymmetrical half-bridge (AHB) DC-DC converter with direct 48V/1V conversion on an e-mode GaN process.
The process only offers four types of devices: LV and HV n-channel e-mode GaN transistors, resistors and capacitors, and the design integrates all the power switches, gate drivers, level shifter, dead time controller and temperature sensor in an active die area of just 4.5mm2.
With many data centre systems moving to 48V power distribution, the demand for higher power for point of load converters to 1V is increasing, and the chip delivers a maximum load current of 5A at 1V output, achieving a current density of 1.1A/mm2 with a peak efficiency is 83.4%.
The AHB topology integrates one high-side and three low-side GaN power switches, one up-level shifter and four gate drivers for a well-balanced 2-phase 48V/1V power delivery design. The circuit can be divided into HV and LV domains, which are naturally isolated by isolation trenches in GaN-on-SOI process.
The primary switches (MH and ML) operate complementarily with a duty ratio. Using the transformer leakage inductance also achieves inherent soft switching on MH and ML for improved efficiency. To optimize zero voltage switching on MH and ML, the dead time during rising and falling intervals can be adjusted.
An on-die temperature sensor monitors hot spots, with the readout signal actively fed into the feedback controller for thermal protection.
To avoid false triggering events and transmit the driving signal robustly, two auto-breakers are built with low voltage (LV) GaN transistors. The breakers automatically protect the GaN devices from potential breakdowns by high voltage (HV) spike, while damping resistors further mitigate interference.
Under standard double-pulse test setup, the gate driver demonstrates 11.6ns and 14ns rising and falling delays. These are among the shortest delays reported for monolithic GaN gate drivers under similar test conditions, say the researchers in a paper at ISSCC 2022 this week, and reduces overall static power by at least 46% to 70mW with half the chip area, despite twice the number of gate drivers.
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