56 Gbps PAM4 SerDes targets next generation switches and routers
Leading OEM customers are presently designing advanced ASIC SoC systems in 28 nm and 16FF+ process technologies utilizing the Avago PAM4 SerDes cores.
PAM4 technology enables future scaling of core/metro router and hyperscale data centers by more than doubling link throughput to 56 Gbps from 25 Gbps, in full duplex per differential pair. Rack-level applications will particularly benefit from PAM4 technology realizing advantages in space, power, cost, and simplified cabling.
The Avago 56Gbps PAM4 SerDes is designed to support a wide range of copper and optical interconnects ranging from chip-to-chip, chip-to-module, low-cost direct-attached cable, and copper backplane down to 35 dB loss. The SerDes supports speeds from 1 Gbps to 56 Gbps, including existing 10G/25G/40G/50G/100G Ethernet, Fibre Channel, and OIF CEI NRZ speeds, providing investment protection and a forward-looking architecture path to networking, compute system vendors, and mega data center companies.
By also targeting emerging OIF CEI-56G-VSR and IEEE 802.3bs (400GE) electrical standards defining next generation chip-to-module interconnect, the 56 Gbps PAM4 SerDes provides the additional benefit of enabling the same PAM4 signaling deployment on front side and back side interfaces, thus increasing SoC use case flexibility and reusability across hardware platforms.
The 56 Gbps PAM4 SerDes, now available in silicon, is running PRBS31 traffic, error-free, across various interconnects up to 56 Gbps, thus reducing ASIC development risk and accelerating Avago customer system deployment.
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