
5G channel equalizer doubles spectral efficiency to reduce cost per bit of O-RAN networks
AccelerComm in the UK has developed a channeliser that doubles the spectral efficiency of 5G open RAN networks, reducing the cost per bit or the energy per bit.
The 5G PUSCH Channel Equalizer module enables significant improvements in O-RAN network performance, and as a result reducing network power and cost per bit.
The module is the latest in a series of hardware channel-based acceleration engines which use AccelerComm’s broad portfolio of optimised 5G Layer 1 IP modules for ASIC and FPGA, to deliver an integrated solution. The Equaliser uses innovative equalisation algorithms to cancel interference from neighbouring sources to double the throughput per Hertz (spectral efficiency) of an operator’s network.
The integration of the PUSCH channel components up to and including the Equaliser module realises further efficiencies in network performance, which translate into power savings through the reduction of the number of sites required to provide high-quality network coverage. The complete 5G PUSCH Channel Equaliser, and its component IP modules, including the Equaliser itself, and the LDPC and Polar encoder/decoder are available as configurable low gate-count IP cores optimised for ASIC or FPGA.
The LDPC module improves network performance through lower error rates, at the same time delivering power savings and over 30% processor resource saving in the 5G physical layer by offloading the LDPC algorithm into hardware.
AccelerComm has also today released a 5G PUSCH Channel Equalizer evaluation tool, which customers can download and use to assess the benefits in their own network, by setting up specific deployment use case parameters and comparing performance with the standard Matlab 5G model.
“Network efficiency lies at the centre of the success of 5G, both in terms of power consumption and the use of valuable spectrum assets,” said Eric Dowek, Segment Marketing Director. “Our innovations in modular 5G Layer 1 IP solutions, implemented efficiently on ASIC and FPGA, help deliver 5G network performance at a price point that makes good business sense.”
