65nm 300mm BCD process for power management chips

65nm 300mm BCD process for power management chips

Technology News |
By Nick Flaherty

The company expects the combination of high volume 300mm wafers and 65nm process technology to bring major performance and cost advantages. The technology is manufactured in TowerJazz’s Uozu, Japan facility, based on the company’s 300mm 65nm automotive qualified flows.

To start, the process includes four power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. Multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance.

The platform provides significant material competitive advantages for any type of power management chip up to 16V regardless of application, including a wide variety of products such as PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers. IHS Markit Power IC Analyst, Kevin Anderson forecasts a $9.4 billion available market, which this technology addresses, in 2018 with continual growth.

The BCD process will offer the highest power efficiency, very small die size, best digital integration capability; and superior cost effectiveness through both the smallest footprint and the lowest mask count.

Mass production is scheduled to ramp up by the fourth quarter, the company said.

For more information on TowerJazz’s 65nm BCD technology, please visit



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