6nm AMD Versal FPGA boosts bandwidth
AMD is launching its second generation of Versal FPGA with double the bandwidth and CXL memory support.
The gen 2 Versal Premium is a monolithic device built on a 6nm process for aerospace and defence, test and measurement and telecoms applications as well as AI data centres. The chip has a new generation of transceiver capable of 128Gbit/s transfers with both NRZ and PAM4 coding to support PCI Express 6.0 links and CXL 3.1 memory interfaces.
“The Versal Premium Gen 2 is all about faster dataflow, higher efficiency and evolving security threats,” said Mike Rather senior product manager adaptive and embedded computing group at AMD.
“This year for the first time DDR5 will overtake DDR4 and we see DDR5 taking a dominant share of the market over the next few years. We see PCIe 6, LPDDR5 and CXL3.1 as key technologies.” The chip also includes support for inline ECC and encryption on the DRAM controllers.
“We are starting to see 6G RAN being built around these platforms and in T&M we see a big push to PCIe 7.0 testing and MIPI C and D PHY camera sensors as well as AI data centres.”
The chip also includes a high efficiency LPDC decoder that saves die area compared to soft logic for satellite as well as for NV memory storage.
In the data centre, the PCIe 6.0 link gives a high performance connection to the Epyc processors and the additional of CXL support brings coherency so that the CPU can see the memory in the FPGA and the FPGA can see the memory in the CPU. This can be used to recover stranded memory and for near memory compute, saving power consumption.
“In AI we see customers building out GPU clusters with high performance networking and FPGAs are the perfect platform for customisable networking interfaces in a scalable ai training cluster,” he said.
“Unlocking more memory capacity is more important than ever. Support for LPDDR5 and DDR5 gives a 2x speed up over gen 1 and saving 20 to 30% lower power at that performance with support for inline ECC and encryption. Then if you max out the bandwidth on all eight 32bit memory interfaces, you can then hook up two 8 lane CXL expansion modules and this gives you 500Gbytes/s of memory bandwidth which previously would have required the Versal HBM device with high bandwidth memory,” he said.
AMD is also updating the Vivado FPGA design tool with new place and route algorithms and multi-threaded performance to improve compile times and enhanced incremental flows that lets designers swap out portions of the logic and segmented config to improve wake up times on PCIe. There is also improved support for RTL and key IP blocks such as the transceiver controller.
The Vivado tool will be updated in 2025 with samples in H2 2025 and production in early 2026.
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