8-bit AVR MCUs gain PIC-style Core Independent Peripherals
With this launch, Microchip says that it is reiterating both its intention to continue full support and development for both PIC and AVR architecture; and its focus on 8bit. 8bit MCUs continue to sell in ever-growing volumes, the company says, and remain an appropriate choice for very many simpler, especially real-time, tasks.
The new series is supported by the START package (that generates ‘housekeeping’ code in C and frees development time for application coding) for graphical configuration of embedded software; it integrates rich features with 4 kB or 8 kB Flash in low pin-count packages; its core independent peripherals include a peripheral touch controller; and has self-programming for firmware upgrades and power-down mode with SRAM retention.
Four new devices range from 14 to 24 pins and 4 kB or 8 kB of Flash and are the first tinyAVR microcontrollers to feature Core Independent Peripherals (CIPs). Micrdochip notes that Atmel had previously implemented a feature very similar to CIPs, in some of its larger MCUs – the Event system. With this series, it has effectively migrated thtatfeature down to the smaller devices. The new devices will be supported by START, a free-of-charge online tool for intuitive, graphical configuration of embedded software projects. The toolset supports new users by assisting the selection of the most appropriate mix of peripherals for a given task.
“This announcement is very important to Microchip as it represents the coming together of the two most powerful 8-bit MCU brands under one roof,” said Steve Sanghi, CEO and Chairman of the Board of Microchip Technology Inc. “Customers love both PIC and AVR MCUs and Microchip is re-energising new product development to not only continue to support, but to grow the AVR portfolio.”
The new ATtiny817/816/814/417 devices integrate features including: a core-independent Peripheral Touch Controller (PTC); Event System for peripheral co-operation; custom programmable logic blocks; self-programming for firmware upgrades; non-volatile data storage; 20 MHz internal oscillator; high-speed serial communication with USART; operating voltages ranging from 1.8 V to 5.5 V; 10-bit ADC with internal voltage references; and sleep currents at less than 100 nA in power-down mode with SRAM retention.
CIPs allow the peripherals to operate independently of the core and include serial communication and analogue peripherals. Together with the Event System, which allows peripherals to communicate without using the CPU, applications can be optimised at a system level. This lowers power consumption and increases throughput and system reliability.