8051 IP core runs 15 times faster
The DP8051 is the fifth generation 8051 IP Core in Digital Core Design’s portfolio, running the Dhrystone 2.1 benchmark program 11.46 to 15.55 times faster as a result of its 300MIPS pipelined RISC architecture.
The speed optimized 8bit soft core is intended to operate with fast (typically on-chip) and slow (off-chip) memories. Broad set of additional features and peripherals let the engineer to tailor the core to the specific application and/or hardware requirements. Moreover, the core has been designed with a special concern about power to performance ratio using an advanced power management PMU unit as well as 2-15 interrupt sources, 4 interrupt levels, 2 data pointers, USB device, Ethernet controller, up to 4 timer/counters, 2 UARTs, 4 I/O ports and more. Depending on the configuration, the designer can choose from compare/capture, watchdog, master/slave I2C Bus controller, Quad SPI, fixed point coprocessor or a floating point coprocessor.
The Dhrystone 2.1 benchmark score for the DP8051 shows speed improvement from 11.46 to 15.55 over Intel’s original 80C51 at the same frequency. The same C compiler was used for benchmarking the core vs. 80C51, with the same settings. This performance can be also used in low power applications, where the core can be clocked over ten times slower than the original implementation, without reducing the performance.
The DP8051, like all other DCD’s 8051 IP Cores, has a built-in support for the DoCD Hardware Debugger, which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, DoCD provides non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). This captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows to improve the size of the IST buffer and extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed and then presented to the user as an ASM code and related C lines.
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