A compact, power-efficient SAR ADC for ultralow-power wireless applications
The need for ultralow-power ADCs
Today’s wireless electronic systems store and process information in the digital domain. For these systems to interface with real-world signals, conversions between the analog and digital signals are required. Therefore, one of the keys to the success of these wireless systems has been the advance in analog-to-digital convertors (or ADCs). To be applicable for wireless standards, such as the 802.15.14g, the ADCs have to meet some stringent requirements: they need to be low power, have a high conversion rate (expressed in mega-samples per second or MS/s) and a high resolution (>10 bits). This resolution indicates the number of discrete values the ADC can produce over the entire range of analog values. Since the values are stored in binary form, the resolution is expressed in bits.
DAC matching, a challenge for accurate designs
Among the many ways of implementing an ADC, the SAR or successive approximation ADC is attractive because of its excellent power efficiency. A SAR ADC uses a comparator to successively narrow down the range that contains the input voltage. A key component in the design of the SAR ADC is an internal digital-to-analog convertor (or DAC) which drives the comparator. But the role of this DAC is also critical, since the accuracy of the SAR ADC is mainly defined by the DAC capacitor matching. This matching is mainly influenced by manufacturing processes and physical design. In modern CMOS technologies, the intrinsic accuracy of the SAR ADC is therefore limited to 10 to 12 bits.
Researchers look for solutions to improve the DAC matching. One way is to scale up the device dimensions, but this is at the expense of power efficiency and speed. Alternatively, calibrations are introduced to correct the circuit imperfections by measuring and correcting the induced errors. These calibrations are mostly implemented off-chip, since the power for the calibration circuit is relatively high when implemented on chip.
Our solution: an on-chip redundancy-facilitated background calibration
Imec and Holst Centre have presented an innovative solution, which successfully implements, on chip, a low-power fully automated background calibration. This calibration utilizes a redundancy-facilitated error-detection and correction scheme.
Introducing redundancy in the analog-to-digital conversion process is another popular solution to deal with errors. It differs from calibration in the sense that the errors are neither measured, nor corrected, but simply tolerated and rejected by the conversion algorithm. Combining calibration and redundancy is often required to make certain calibration techniques work. In our design, the redundancy not only facilitates the proposed background calibration, it also relaxes the DAC settling requirements and saves power by using a two-mode comparator.
The proposed ADC uses a total of 15 cycles to perform a 13 bit conversion. The two-mode comparator works in low-power mode first (mode 1), and switches to high-precision mode (mode 2) in the last 5 cycles, resulting in a two-fold energy reduction. However, two errors are still present. First, the DAC matching is limited to <10 bits, which is due to the presence of small elements (0.3 fF) used in the DAC capacitor to save area. Second, a dynamic offset occurs when the comparator switches from mode 1 to mode 2.
The automated background calibration successfully suppresses both errors, with negligible overhead in area or power. The calibration logic is only enabled for a limited set of SAR codes which are suitable for DAC or comparator calibration. As a result, the large initial DNL (or differential non-linearity) errors caused by the dynamic comparator offset are effectively reduced, and the INL (or integral non-linearity) errors due to DAC mismatch are suppressed.
Figure ADC architecture: The ADC architecture, including the comparator, the SAR logic, the feedback DAC and the calibration logic. Click image to enlarge.
Figure ADC chip: Photo of the ADC chip.
An ultralow-power 6.4 MS/s 13 bit ADC in 40nm CMOS
By using this innovative design, the researchers at imec and Holst Centre have realized a 6.4 MS/s 13 bit ADC in 40nm CMOS. Thanks to the low-power calibration, this ADC achieves an effective number of bits (or ENOB) of 10.4 bit and a state-of-the-art power-efficiency of 5.5 fJ per conversion step at 6.4 MS/s. Overall, the chip consumes 46 µW from a 1 V supply. The ADC achieves 64.1 dB SNDR (or signal-to noise and distortion ratio). In combination with the ENOB, this gives a good indication of the overall dynamic performance of the ADC. When compared to similar work, our ADC achieves the best power efficiency, while also integrating, on chip, a background calibration technique for comparator offset and DAC mismatch.
Figure ADC results: Performance summary and comparison with state-of-the-art. Click image to enlarge.
What’s in it for industrial partners?
Imec and Holst Centre’s SAR ADC is available for interested parties through IP licensing. For more information, visit www2.imec.be/be_en/research/wireless-communication/ultralow-power-wireless-communic.html.