A future-proof design engine for Altera’s FPGAs
Now customers can design and implement at higher levels of abstraction for significantly faster design cycles to meet the next generation of design opportunities. The Spectra-Q engine features faster algorithms and allows for incremental design changes without needing to perform a full design compile.
It also features a hierarchical database that enables users to preserve placement and routing information of IP blocks while making changes in other parts of the design. This helps ensure stable designs, eliminates unnecessary timing closure efforts and reduces compile times.
Built on top of the Spectra-Q engine is an industry first platform design tool called BluePrint that allows designers to perform architectural exploration and assign interfaces with greater efficiency. The tool reduces design iterations by 10X by allowing designers to explore and create legal IO placements up-front with real-time fitter-checking. The tool also includes a clock and core planning feature that greatly reduces the number of design iterations needed for timing closure.
In addition to providing support for the latest HDL languages, the new engine is designed to support Altera’s new A++ Compiler for HLS (high level synthesis) to create IP cores from C or C++ which significantly boosts productivity through faster simulation and IP generation. The new engine is integrated in the Quartus-II Software and IP Version 15.0 just released.
Both the Subscription Edition and the free Web Edition of the Quartus II software v15.0 are now available for download at https://www.altera.com/download.
More information about the Spectra-Q engine at https://www.altera.com/spectraq
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