A load store architecture for any quantum computer
Researchers in Japan have created the first fault tolerant load store architecture that works for any quantum computer.
This is the first use of a load-store-type structure and can reduce resource requirements of quantum computers by approximately 40%. This overcomes the scaling, memory utilization and portability issues of conventional, quantum-circuit-based designs and marks a key step to a general purpose machine.
The researchers with NTT, tThe University of Tokyo, Kyushu University and RIKEN developed the load store quantum computer architecture (LSQCA) that would allow programs to be easily ported between machines in the same way as today’s classical computers. As the architecture is defined as an abstracted form, it can be applied to a wide range of qubit devices, connectivity configurations, logical operations methods, and error-correcting codes.
- Record $230m for neutral tom quantum computer
- Quantware raises €20m for 1m qubit quantum computer
- PsiQuantum shows quantum chips
Conventional quantum computer designs apply quantum circuits where the programs are expressed and executed from computable registers, where the quantum data is stored. This presents a challenge for scaling up as the computer must be expanded while maintaining the ability to perform arbitrary basic operations on all data, no matter where the data is stored on the device. These programs are also optimized specifically for the size of the devices and the error correction method, making it difficult to port executable files to computers even with slightly different configurations.
In a load-store architecture, the device is divided into a memory and a processor to perform calculations. By exchanging data using two abstracted instructions, “load” and “store,” programs can be built in a portable way that does not depend on specific processor or memory device structures. Additionally, the memory is only required to hold data, allowing for high memory utilization.
This can be considered as a hierarchical memory subsystem that ensures the scalability of memory capacity while suppressing average access latency. Static analysis of the memory reference patterns for fault tolerant quantum computer algorithms found that they have access locality, which can be exploited in the load store architecture.
The idea behind the architecture is to separate the whole memory regions into small computational space called Computational Registers (CR) and space-efficient memory space called Scan-Access Memory (SAM). The instruction set architecture of LSQCA leads to two types of designs compatible with surface-code-based FTQC: point-SAM and line-SAM architectures, exhibiting different characteristics in terms of memory efficiency, latency, and the utilization of access localities.
The paper describing the load store architecture is here
Load-store computation is often associated with an increase in computation time due to the limited memory bandwidth between memory and computation spaces. By proposing new quantum memory methods such as row access type and point access type, the researchers provide a theoretical 100% memory efficiency with approximately 90% efficiency can be achieved in practical cases. This approach successfully reduced the computation time increase to approximately 5% compared to today’s quantum computer that can perform calculations in the entire area of the computer.
The researchers defined an instruction set for these abstract structures and provided concrete designs named point-SAM and line-SAM architectures. This can improve the memory density by allowing variable-latency memory access while concealing the latency with other bottlenecks.
Optimization techniques can exploit properties of quantum programs observed in static analysis, such as access locality in memory reference timestamps.
The performance and the execution time overhead of LSQCA were evaluated by numerical simulations with realistic quantum programs and various configurations. The results show that LSQCA achieves higher memory density than conventional floorplans with a negligible or modest increase in execution time.
The team now plans to work on a more sophisticated instruction scheduler to handle variable memory-access latencies introduced by the LSQCA that can further minimize the memory access overhead. For example, variable memory access latencies might be efficiently concealed by using techniques commonly employed in conventional computing such as strategic data allocation or prefetching.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
