A new generation of microcontrollers: Jumping ahead to 40-nm process technology – part 1
MCUs today are the heart of many automotive features. For example, automotive MCUs implement safety features, make possible environmental friendliness, and provide convenience, comfort, connectivity and entertainment for drivers and passengers. For that reason, it is not unusual for a typical mid-priced new car to contain hundreds of MCUs spanning a range of processing and communication capabilities.
Going forward, even larger numbers of embeddable MCUs will be needed to meet the growing number of standard and optional electronically controlled capabilities required by regulators and desired by car buyers. These design requirements will necessitate chips with greater functionality.
Flash-memory manufacturing technologies are critical to microcontroller (MCU) design. Renesas has become the first in the industry to develop a 40-nm generation production process for MCU-internal flash memory. By jumping directly from today’s 90-nm generation process all the way down to a 40-nm one, we have leapfrogged the entire 65-nm processing generation to enable new devices with unprecedented features and capabilities. In this story Dr. Hideto Hidaka, General Manager of our Embedded Memory Core Development Division, Technology Development Unit, describes the new breakthrough technology, its development background, and its likely impact on our products and the industry.
Providing the fast-access flash memory required by high-performance MCUs
As the control capabilities of embedded systems become increasingly beneficial and sophisticated, today’s consumers are seeking more than just greater convenience, better ease of use, and high reliability in their new cars and other major purchases. They are also demanding functional safety, product security, and networking capabilities, among other features. To meet these needs, system engineers are seeking advanced microcontrollers (MCUs) that deliver fast operation, offer broad support for peripheral functions, and can accommodate large-scale and powerful built-in programs.
High-performance MCUs therefore must include large internal flash memories for storing complex control algorithms and application code. Being a world-leading MCU maker, Renesas has a continuing goal of achieving ever-greater on-chip flash capacities while keeping MCU costs down.
Not only must the on-chip flash memory have a large capacity, but it also has to have a fast access speed so the CPU can fetch stored digital information quickly in order to maximize program execution. The high-speed logic circuits of high-performance MCUs cannot work at their full potential if the memory access speed is slow. Obviously, CPU clock cycles should not be wasted waiting for data to come from memory. Obtaining the fastest possible flash access speed is essential to improving application performance and simplifying system design.
Renesas has consistently maintained a decisive industry lead in access speeds for built-in MCU flash memory. As far back as 2004 we achieved an extraordinary 100-MHz internal flash memory speed, even though we were then using 150-nm generation processes. The highest speed that other MCU vendors’ MCUs could deliver at that time was limited to about 40 MHz.
Since then our technology has advanced. As Figure 1 shows, after launching the fast 150-nm generation internal flash memory in 2004, Renesas advanced to the 90-nm generation in 2007—an industry-first achievement that allowed much more memory capacity. The 90-nm generation, 100-MHz internal flash remains a key feature of the MCUs we ship today.
Needless to say, other MCU suppliers have been climbing the process technology curve, too. What is significant, though, is that with regard to on-chip flash memory, they haven’t been able to catch up with our technology. Their MCUs still generally can’t deliver access speeds in excess of about 40 MHz and thus those chips suffer big performance disadvantages.
Figure 1: Timeline of Renesas MCU developments and internal flash memory operating speeds.
Using our internally developed memory-cell technology to deliver superlative flash reliability
Besides semiconductor process technology, on-chip flash memory density and speed are determined by memory cell design. This is a key area in which Renesas maintains a competitive edge.
The foundation of our exceptionally fast, very dense internal flash memory is an independently developed MONOS (Metal Oxide Nitride Oxide Silicon) cell technology. Each transistor in the flash cell consists of three layers—oxide, nitride, and oxide—on a silicon base, with a metal control gate at the top. Data is stored by changing the transistor’s threshold voltage, the voltage at which the transistor turns on. That variation, which defines the presence of a ‘1’ or a ‘0’, is determined by the amount of electrical charge captured in the nitride layer.
This Renesas-exclusive design differs in important respects from the typical built-in flash memory, which uses traditional floating-gate technology (see Figure 2). Importantly, our MONOS implementation has the advantage of much better scalability and enhanced reliability.
In a typical floating-gate cell design, any leak in the gate-oxide layer will allow almost all of the cell’s stored charge to escape into the substrate. With our MONOS design, however, only the charge close to the point of leakage escapes; most of the charge—and therefore the data—is retained. That major charge-leakage reduction both boosts the reliability of the flash memory and also facilitates design efforts to shrink the memory cell size in both the vertical and horizontal directions.
Renesas’ MONOS flash technology is particularly well suited to automotive and other high-end applications that demand MCUs with increased levels of integration and high reliability. The excellent performance of our flash MCUs has been tested and proven by millions of hours of error-free operation over extended periods of time.
Figure 2: Comparison of MONOS and traditional floating-gate flash cell technology.
Creating a fast, power-efficient split-gate cell for MCU flash memory
Renesas has accumulated more than two decades of experience in the use of MONOS flash memory technology by providing MCUs for smart cards, the highly secure and reliable IC cards widely used around the world for financial transactions. Recently our expert R&D teams have successfully extended the technology by developing a split-gate structure suitable for MCU internal flash memory. The new cell design approach divides the gate into two parts (see Figure 3). One part is used as a memory-cell select function and the other part is used for storing data.
In this innovative split-gate, one-and-a-half transistor design, the select gate is normally off (that is, it’s in the OFF state when at 0V), whereas the memory gate is normally on (i.e., it is the ON state at 0V). The select gate is implemented with a short channel. Additionally, the oxide layers on the split gate are very shallow, as thin as those on logic circuits. These design techniques produce a scalable flash memory cell that is faster and uses less current than memory cells built with standard gate structures.
Figure 3: Fast, low-power split-gate memory cell with cell-select and data-storage functions.
Jumping well beyond the next-generation process technology
At present, Renesas continues to introduce new industry-leading flash MCUs built with our well-proven 90-nm generation semiconductor process technology. Like other companies in the field, we previously had investigated transitioning to a new generation of processing equipment that applies technologies between 65 and 55 nm generations, the progression suggested by conventional production wisdom. In fact, just before NEC Electronics and Renesas Electronics merged to form today’s Renesas, both firms had independently developed 65/55-nm generations flash memory capabilities and were one step away from separate next-generation product launches.
The April 1, 2010 merger changed that plan, however, into a far bolder manufacturing strategy. Renesas management created a forward-looking plan to consolidate our corporation’s synergistic chip-design and process-technology strengths and apply them to the task of leapfrogging the 65-nm generation process. That is, they decided to transition our flash MCU production directly from 90 nm to 40 nm generations. Doing so would allow us to break through the semiconductor industry’s technology assumptions and widen our lead in competitive global MCU markets.
Accordingly, we announced in December 2011 that we were developing 40-nm generation flash memory for use in our MCUs. We expect to ship samples of 32-bit MCUs incorporating this new-generation of on-chip memory in the latter half of 2012.
The change from a 90-nm to a 40-nm generations process will have major benefits that customers can apply to new products. Our 40-nm generation MCUs will have more than double the maximum flash memory capacity of our 90–nm generation devices, thus accommodating bigger control and application programs. At the same time, we will be able to offer MCUs with nearly four-times as many logic-circuit transistors. This will facilitate boosts in processing capabilities and the incorporation of more and better built-in peripheral functions.
The newly developed flash memory will come in two types: code (program) memory and data memory. The code memory will run at high speed: 120 MHz. The data memory will deliver 20-year data retention and have an operating life of 125,000 write cycles.
Reliability at high temperatures will be another advantage favoring the upcoming 40-nm generation flash MCUs. This feature is certain to be of particular interest to automotive industry firms.
Engineers designing new cars and trucks have a great need for high-performance MCUs that can reliably read from and write to the built-in flash memory over a wide span of temperatures—especially at high temperatures. Our next-generation MCUs will handle ambient temperatures up to 125ºC and junction temperatures up to 160°C. The excellent high-temperature performance will help ensure application reliability even when the devices are mounted near a vehicle’s engine compartment. Figure 4 summarizes key target performance specifications for our upcoming 40-nm generation MCUs.
The data is extremely conservative. That’s because Renesas, like other manufacturers of high-reliability products, must be very careful not to overstate design specifications. Our restraint is most obvious in the write cycle specifications. Whereas we will guarantee that the code-storage flash memory will withstand 1,000 write cycles, in practice it will actually support 1 million write cycles.
During the development of the 40-nm generation flash memory, our chip R&D experts revised all of our design specifications. Importantly, the reductions they have achieved in the memory’s silicon surface area will allow us to deliver built-in MCU flash capacity at a very competitive per-unit cost.
Part 2 will describe in detail the new RH850 MCU family for automotive applications.
About the author: Hideto Hidaka is General Manager, Embedded Memory Core Development Division of Renesas Electronics’ Technology Development Division.
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