A rethought PIC IP Core – the DRPIC1655X – for FPGA or ASIC, with PIC compatibility
DCD says that thanks to its price and software simplicity, engineers can minimise software development costs and enable easy portability across low to high-end platforms. DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast, dual ported memory.
It’s been designed with special attention to low power consumption,for an optimal power, price and performance combination. The company sees it as suiting IoT projects where, according to Jacek Hanke, DCD’s CEO, efficient solutions like DRPIC1655X are the right answer, as they can be implemented for less than $1 in 10k quantities. An FPGA netlist is also available.
The DRPIC1655X MCU fits applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power-save mode makes this IP core suitable for applications where the power consumption aspect is critical.
The DRPIC1655X soft core is software-compatible with the industry standard PIC 16XXX (8-bit) MCUs. It implements enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by the multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory.
The DRPIC1655X architecture is four-times faster than the standard architecture. Most instructions are executed within one system clock period, except for instructions which operate directly on PC (GOTO, CALL, RETURN) program counter; this situation requires the pipeline to be cleared and subsequently refilled which takes additional one clock cycle.
The DRPIC165X is delivered with a fully automated testbench, complete set of tests and DoCD on-chip hardware debugger, which allow easy package validation, at each stage of an SoC design flow.
Unlike other on-chip debuggers, DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.
CPU features include;
Software compatible with PIC16C55X industry standard
Pipelined Harvard RISC architecture
4 times faster, compared to original implementation
35 instructions
14 bit wide instruction word
Up to 32 kB of internal Data Memory
Up to 64 kWords of Program Memory
Configurable hardware stack
Power saving SLEEP mode
Fully synthesisable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Technology-independent HDL Source Code
800 MHz virtual clock frequency in a 0.35-micron process
DCD; https://dcd.pl/ipcore/81/drpic1655x/
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