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Accelera group to create mixed-signal interface SystemVerilog extension  

Accelera group to create mixed-signal interface SystemVerilog extension  

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By Nick Flaherty



The Accellera Systems Initiative has formed a working group to tackle a key challenge for mixed signal system on chip designs.

The Working Group for SystemVerilog Mixed-Signal Interface Types (SystemVerilog MSI) aims to create a standard for interconnects between dissimilar net types, including bidirectional connections.

Past efforts to add similar functions to mixed signal design tools outside the IEEE 1800 standard, such as Verilog-AMS connect modules, have proven unable to address the complexity and usability requirements that have arisen in typical System-on-Chip designs. 

Over time various limitations have had to be addressed by EDA vendors, a key issue for chip designers in Europe. The SystemVerilog MSI Working Group is tasked with resolving these issues to create a standard across the industry.

 “Accellera continues to look for opportunities to develop standards that will improve design and verification productivity for electronic product development,” said Lu Dai, Chair of Accellera. “The SystemVerilog MSI Standard will create efficiencies for engineers using the upcoming Verilog-AMS and UVM-MS (formerly UVM-AMS) standards by making it easier to connect analog and mixed-signal models to SystemVerilog designs.”

The new working group will be chaired by Tom Fitzpatrick, who is also Chair of the UVM-MS and IEEE Std 1800 working groups, and co-chaired by Peter Grove, who is also the SystemVerilog-AMS Working Group Chair and UVM-MS Co-chair.

“Our goal is to release this new standard as an addendum to IEEE Std. 1800-2023,” said Fitzpatrick. “Vendors will be able to rely on this new standard to implement the functionality quickly to provide users a reliable platform with which to model and simulate complex mixed-signal design and verification environments.”

 “We expect this new functionality to enable the SystemVerilog-AMS standard to bypass some limitations that were present in Verilog-AMS,” added Grove.

The Accellera UVM-MS and SystemVerilog-AMS Working Groups have shown that there is a fundamental need for support of bidirectional net connections between logic/UDN (User-Defined Nets) and analog/electrical/real signals as an integral part of IEEE 1800.

The first meeting of the new working group is planned for mid-March. There is more information on the SystemVerilog MSI Working group on the working group page.

www.accellera.org

 

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