Accelerate time to market by saving ESD test time
Electrostatic discharge (ESD) qualification processes have become complex and expensive with the increased cost of ESD test time due to the industry trend toward higher package pin counts for ICs. This increasing demand for routine ESD testing of every pin can be mitigated by testing only a fraction of the pins while preserving the same data quality from the test results.
To reduce test times, increase qualification speed and preserve accuracy, an intelligent sampling method can be applied to groups of pins that share the same applications. Not only does the proposed method help accelerate time to market, it builds a bridge amongst the commonly disconnected disciplines of statistics, design and test engineering.
Test time complexities
As a part of IC product qualification, test times and test resources have become an increasing burden during evaluation for ESD. Therefore, a new approach would not only be unprecedented, but also it could lead to a venue of new ways for obtaining critical information in an expedient manner.
For semiconductor IC designs, it is now common practice to implement identical IO pins (clones) that have the same function with the same exact ESD protection cell. The clones share the same buffers and have the same macro name to identify them. In some cases, their population can be up to 70 percent of the total pin count for the device. The benefit for test time saving is significant for these cases, especially when the IC package pin counts exceed 3000.
Statistical methods for ESD
Statisticians and industrial engineers have long known how to estimate the sigma of a population using the range from a sample, assuming the data comes from a normal distribution [1]. The expected value of the range is proportional to the sigma (Fig. 1).
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The proportionality constant increases as the size of the sample increases. Using the sample range as a proxy for the population sigma is convenient and easy, forming a desirable heuristic, and is commonly used in semiconductor statistical process control analyses.
Testing the sample range is ideal if failure levels are assumed to be normally distributed. The central limit theorem says that a superposition of independent random variables tends toward normality, regardless of the distribution of the random variables contributing to the sum. The many physical variations manifested in an ESD reading may average out, leading to normally distributed ESD readings. In a recent study, the ESD readings from the identically designed pins appear to come from a normal distribution [2]. Figure 2 shows a typical distribution.
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For a possible application of sampling, one has to accept that all of the untested pins (i.e. untested clones) would give similarly distributed readings as the selected pins. But for the method to work, such distributions have to be established relative to the desired lower specification limit (LSL). The process for ready application of sampling becomes more practical when the LSL and sampled readings are farther apart (Fig. 3).
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A practical method
Ideally, if the sampled ESD readings are bounded from above and below, with a gap between the smallest readings and the LSL, then one can make inferences regarding the pins that were not sampled. Statistical confidence statements can be made with regard to the proportion that is likely to fall below the LSL among the pins that were not sampled.
An applied sampling method has to be simple and practical. First, the failure distribution of the clone pins should be Gaussian in nature with a reasonably tight range (R) as determined by the distance between the maximum voltage where all pins still pass (V1), and minimum voltage where all pins fail (V2). With this value of R, the Sigma (σ) for the distribution can be estimated.
But how many data readings are necessary? From known statistics for normal distribution, the expected value of the range is a multiple of σ with the multiple as a function of the count of readings. It turns out that 30 is a practical count for which the range R would be within about four sigmas (Fig. 1). For distributions that are Gaussian in nature, the Min voltage and the mid-range voltage where half of the pins fail (VM) can be used with equal accuracy (Fig. 2). Find the V1 and VM values by simply selecting 30 random clones and testing until half of them fail. The number of sigmas that can fit between LSL and VM determines the cumulative distribution function (CDF) at the LSL (Fig. 3). The CDF at the LSL represents the proportion out of the specification for each sampled pin.
The final step is to extend the probability to insure that all the unmeasured pins still are above LSL with a confidence level of 99 percent. In summary, this approach enables information collected on just 30 identical pins to be used to determine the required sampling number with a confidence level of 99 percent such that all cloned pins are validly represented by our ESD test sample.
ESD sampling
To use the proposed method, failure data has to be collected on the identical clones sample with stepped voltages until half of them fail. For the cloned IO pins, their ESD failure distributions will follow a common behavior since the same protection device governs their failure levels. Some variations are expected due to physical differences in the IC layout and the failure thresholds derived by thermal limits due to process effects. Sampling is applied once conditions are met.
To illustrate, suppose there are N clones and 30 are selected to measure the maximum voltage point where none of them fail (V1) and the voltage point where half of the 30 pins fail (VM). The range is estimated as twice the difference between VM and V1. The range and the distance from LSL to VM can be applied as described above to find the required sampling, n, for a confidence level of (1-α). Application of this method has shown that if V1 is 2X of LSL, only about 10% of the clones need to be used for ESD testing (Fig.4).
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In general, the farther away V1 is from LSL and the tighter the range, the better the benefit from sampling (Fig. 4). Significant test time savings can be achieved for IC products comprised of hundreds of clones without compromising ESD test accuracy.
Test time savings
The reason to sample is to save time and money. But even more important is the savings in qualification time and improving time to market. For example, it is often the case that when large numbers of identical pins are tested for ESD, the spurious variations that can result in the data cannot be replicated a second time or a third time. The probability for this to occur increases as the pin count increases, so the first step in intelligent testing is to remove these uncertainties and focus on the real issues.
Interdisciplinary efforts and the future
This new ESD sampling, presented at the 2012 ESD Symposium, was developed by a joint committee of ESD Association Standards representing several major IC suppliers and included inputs from people with engineering and mathematical backgrounds. The collaboration among various disciplines is an example of the path necessary to take in order to succeed in the increasingly competitive semiconductor industry landscape. There is a need for interdisciplinary scientific development similar to the paradigm existing among departments at most major universities. The Joint Electron Devices Engineering Council and the ESD Association Standards have preliminarily accepted the intelligent sampling method, pending an official documentation for ballot approval.
References
[1] Grant and Leavenworth, Statistical Quality Control, McGraw Hill Series.
[2]. C. Duvvury, J. Dobson, R. Gauthier, E. Grund, B. Carn, W. Stadler, J. Miller, T. Welsher, R. Gaertner, S. Ward, M. Chaine, A. Righter, “Sampling Pin Approaches for ESD Applications,” Presented at the EOS/ESD Symposium, September 12-14, 2012, Tucson, AZ.
About the authors
Charvaka Duvvury is a Texas Instruments Fellow and an IEEE Fellow, working in the Advanced CMOS Technology Development. He is also a member of the Board of Directors for the ESD Association since 1997. His current work is on development and company wide support on ESD for the nanometer submicron CMOS technologies. Charvaka is co-founder and co-chair of the Industry Council on ESD Target Levels whose mission is to establish safe and realistic component ESD target levels while meeting the silicon technology challenges.
Joel Dobson has been working at Texas Instruments for 21 years where he is a Distinguished Member of the Technical Staff. He is currently working as a corporate statistics expert with specializations semiconductor reliability, quality control and statistical modeling. Dobson is an Accredited Professional Statistician of the American Statistical Association and certified as a Quality Engineer, a Six Sigma Green Belt, and a Six Sigma Black Belt from the American Society of Quality.
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