Accelerated regression testing of mixed-signal SoCs in Synopsys’ verification plans
Synopsys’ initiative to accelerate the verification of mixed-signal system-on-chip (SoC) designs launches with initial elements that include a SystemVerilog-based methodology, AMS Testbench; and the new VCS AMS mixed-signal verification solution that incorporates VCS functional verification and the CustomSim FastSPICE simulator. The VCS AMS solution enables advanced functional and low-power verification combined with performance and capacity for faster mixed-signal SoC regression testing.
A growing proportion of SoCs include digital and analogue blocks from internal and third-party IP sources. The increasing use of sub-nanometer geometries also introduces process variations that increasingly affect circuit performance. The time and compute power required to verify these complex mixed-signal SoCs may exponentially increase the total cost of design. By deploying its VCS AMS mixed-signal verification solution, Synopsys claims, design teams can achieve the throughput and accuracy they require to simulate today’s complex mixed-signal SoCs. However, as mixed-signal SoC complexity grows, “there is a new verification crisis on the horizon that requires additional focus on the overall verification methodology.”
Coverage-driven digital-centric verification methodologies, such as the industry-standard Universal Verification Methodology (UVM), are broadly deployed. Such methodologies enable rapid development of constrained-random testbenches that can be run in parallel across compute farms to reduce overall turnaround time. Synopsys’ AMS Testbench methodology removes a major productivity barrier in mixed-signal verification by extending these advanced techniques beyond the digital domain. Among the extensions provided with AMS Testbench are: constrained-random stimulus for analogue signals; shaped source voltage generators; analogue checkers and assertions; reference model integration with multiple abstraction levels, including SPICE and SystemVerilog; analogue node sampling and monitoring; electrical-to-real data converters; SystemVerilog real number modelling; and analogue functional coverage. Synopsys’ AMS Testbench methodology extensions are complemented by native integration of advanced functional and low-power verification technologies available with the VCS AMS solution to boost throughput. Among the native technologies enhanced for mixed-signal verification are voltage-aware simulation driven by UPF-defined power intent specifications, SystemVerilog real number modelling and assertion checking. By building on the proven UVM standard, AMS Testbench enables design teams to rapidly extend their existing verification environments for mixed-signal SoC regression testing.
The VCS AMS mixed-signal verification solution provides access to VCS functional verification and the CustomSim FastSPICE simulator, and is expected to be available in calendar Q2 of 2014.
Synopsys; www.synopsys.com
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