Accurate compact thermal models of three-die power packages

Accurate compact thermal models of three-die power packages

Technology News |
By eeNews Europe


Thermal management of electronic systems is becoming more important in a wide variety of electronic applications — including computers, telecommunications equipment and semiconductor devices, as well as aerospace, automotive and consumer electronics.  Compact Thermal Models (CTM) of electronic packages is needed in thermal simulations of electronic systems.  A CTM does not disclose the IP information of a package and is preferred by electronic package manufacturers for use in their customers’ thermal evaluation of electronic packages.  On the other hand, a CTM consists of fewer elements than a Detailed Thermal Model (DTM) does, and hence needs less computation time in thermal simulation.

In 1989, an extension of the junction-to-case thermal resistance methodology created a thermal resistance network from junction to each distinct external surface of an electronic package [1].  In 1995, the DELPHI consortium published the first paper on Boundary Condition Independent models [2].  A lot of papers on this topic have been published since then.   JEDEC also published standard of DELPHI Compact Thermal Model Guideline [3] and Two-Resistor Compact Thermal Model Guideline [4].  Many previous publications on this topic including the two JEDEC standards are presented for only single-die packages.

CTMs of SupIRBuck® Regulators offered by IR can give accurate temperature prediction for the three dies in the package.  These CTMs are boundary condition independent.  It means when boundary condition changes, e.g. with or without heat sink, or with different PCB layout under the package, the CTMs can predict the junction temperature rise within 5% difference or better from that of the DTMs.

These CTMs are also independent of power loss distribution inside package.  A typical SupIRBuck® Regulator wire bonding diagram is shown in Figure 1, where Q1 is high-side FET, Q2 is the low-side FET and IC is control IC.  In different application, the power loss distribution among the three dies is different.  For example, when the switching frequency is higher, Q1 adds more power loss than Q2 does.  Different input and output voltages and currents also have different impacts on the power losses of Q1 and Q2.

We use the power loss ratio of Q1 over Q2 together with the total power loss of Q1 plus Q2 to represent the different power loss distribution between Q1 and Q2.  IC has only relatively small change in power loss for different applications.  For these different power loss distributions, the CTMs of SupIRBuck® Regulators can also predict the die temperature accurately in comparison to that of the DTMs.

Figure 1: Typical wire bonding diagram of a SupIRBuck® Regulator

The compact thermal model construction
This Compact Thermal Model consists of three parts: the lead-frame, the top-mold and the model core between them as shown in Figure 2.  The lead-frame is a metal part with some of ordinary molding material; the top-mold is of ordinary molding material.

Figure 2a: Compact thermal model of a SupIRBuck® Regulator


Figure 2b: Side view of the compact thermal model
The model core is actually a thermal resistor network connecting the three virtual junctions, the top-mold and the lead-frame as shown in Figure 3.  Based on our thermal analysis for each of packages, the thermal resistor network is created using ANSYS® Icepak® general network project.  The three junctions represent the three dies in the package.

Figure 3: Model core of the compact thermal model

Result and comparison

A sample model CFD (Computational Fluid Dynamics) simulation result obtained using ANSYS® Icepak® is presented below in the form of comparison between the CTM and the DTM of the package.  The simulation was done with the package model mounted on a detailed PCB thermal model.  The DTM of package used in the comparison had been validated by achieving good agreement with real test data.

Normal boundary condition comparison: The first comparison was made under normal condition of applications with an evaluation board, for different power loss distributions between Q1 and Q2, with and without a heat sink.  In Table 1, the power losses are 2.6 W for Q1 plus Q2, and 0.32 W for IC; the airflow velocity at the inlet is 200 LFM; the ambient temperature is 25 °C, where Q1/Q2 is the power loss ratio of Q1 over Q2.  The heat sink is aluminum with dimensions of W x L x H = 13mm x 23mm x 16mm.  The highest temperature among the three dies is taken as the junction temperature of the package, which is highlighted by the red values in the table. The blue values represent cooler device temperatures for a given simulation.


Table 1a: Temperature comparison of Q1

Table 1b: Temperature comparison of Q2


Table 1c: Temperature comparison of IC

The agreement between predictions of the CTM and DTM is excellent for all the three dies; with the largest junction temperature rise difference of only 0.8%, and the rest die temperature rise difference within 2%.  When the power loss ratio Q1/Q2 changes from 1.6 to 0.625, the CTM temperature prediction accuracy almost remains the same.  With or without heat sink, the CTM’s prediction accuracy almost remains the same.

Extreme boundary condition comparison: The second comparison was made for some extreme conditions of solders under package.  In Figure 4 the two extreme cases are shown beside the normal solders: one is the solder below Q1 voided; and the other is the solder below Q2 voided.  Solder voids could appear in mass production process, but the extreme void conditions happen only if the manufacturing procedures have certain problems.  The voids make it difficult to transfer heat from the above die to PCB.

Figure 4: Solder pad void under package

Table 2 gives the CFD simulation result comparison for these two solder void cases with and without a heat sink.  In the comparison, Q1/Q2=0.625 for the all 4 cases.

Table 2a: Temperature comparison of Q1


Table 2b: Temperature comparison of Q2

Table 2c: Temperature comparison of IC
In the above comparison for extreme cases of solder voids, the agreement between the CTM and the DTM is also very good, with the largest junction temperature rise difference of 3.2%, and the rest die temperature rise difference within 1.4%.

Figure 5 shows that the PCB temperature distributions under the DTM and the CTM are almost identical.  This also indicates that the CTM is a very good replacement of the DTM in thermal simulations.

Figure 5: PCB temperature under DTM (left) and under CTM (right) of case 3


1) Different under-package PCB layouts: The second comparison in Table 2 can also be seen as the comparison for extreme PCB layout cases, in which Q1 or Q2 has a very poor under package thermal cooling due to a poor layout design.  So this comparison also shows that the CTM is independent of different PCB layouts.

2) Model validation and error estimate: The results show that the CTM is highly independent of boundary condition, and it is also independent of power loss distribution between Q1 and Q2.  Therefore the set of practical condition used in this model comparison should be sufficient for the model validation in practical applications.  Meanwhile the comparison can also be used as an error estimate reference.

3) Further simplification:
The CTM of SupIRBuck® Regulator reduces the number of elements by more than half compared to the DTM at the initial simulations.  For end customer’s system simulations, further simplification can be achieved by generating a two-resistor CTM.  When PCB layout is completed, the distributed thermal resistance under package will be fixed; and then an accurate two-resistor CTM, specific for the PCB and a fixed die power loss distribution, can be generated by matching its result to that of the CTM of SupIRBuck® Regulator.


The CTM of SupIRBuck® Regulator shows a high level of boundary condition independence and die power loss distribution independence.  It can predict temperatures of all the three dies accurately at a same simulation.

A set of practical boundary condition has been used for comparison between the CTM and the DTM of SupIRBuck® Regulator.  The comparison serves as model validation as well as an error estimate reference.  A very good agreement has been achieved.  For the normal boundary condition, the largest junction temperature rise difference is 0.8%; while for the extreme boundary condition, the difference is 3.2%.

The CTM of SupIRBuck® Regulator has reduced the number of elements by more than 50% compared to the Detailed Thermal Model in initial CFD simulations.  It can be used by end customers to generate the two-resistor CTM for further simplification in their system simulations.


The authors appreciate ANSYS® engineers’ technical review and feedback, IR Ramesh Balasubramaniam’s review and feedback and IR Wenkang Huang’s help in literature search.


[1] A. Bar-Cohen, T. Elperin, and R. Eliasi, “Theta_jc characterization of chip packages-justification, limitations, and future,” IEEE Trans. Compon., Hybrids, Manufact. Technol., vol. 12, no. 4, pp. 724–731, Dec. 1989.

[2] Lasance C., Vinke H., Rosten H., Weiner K.-L., “A Novel Approach for the Thermal Characteri-zation of Electronic  Parts,” Proc. of SEMITHERM XI, San Jose, CA, pp. 1-9 (1995)

[3] JEDEC Standard “DELPHI Compact Thermal Model Guideline,” JESD15-4, October 2008

[4] JEDEC Standard “Two-Resistor Compact Thermal Model Guideline,” JESD15-3, October 2008

Note: ANSYS and Icepak are registered trademarks of ANSYS corp.

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