Achieving high analog-IC performance via specialized foundry processing
Today’s electronic products demand higher and higher levels of performance and precision. These products range from those we deal with every day, such as mobile handsets, audio systems, and HDTVs, to those we interact with only indirectly, like CT scanners and industrial control systems. Most of these systems rely on some form of digital microprocessor or DSP as the computational engine. However, each of these products derives their ‘personality’ – i.e., their differentiating features – from the high-performance analog chips inside.
Behind these analog ICs is usually a specially-crafted IC process technology that optimizes performance and precision. Since such specialty processes are designed from the outset for performance and generally not intended for routine, cost-sensitive applications, they typically drive the creation of standalone devices with unique characteristics. With the relentless march of technology, such standalone designs eventually become widely used within System-on-Chip (SoC) implementations.
Significantly, high-performance analog CMOS processing, once the exclusive domain of integrated device manufacturers (IDMS) is increasingly accessible through specialty foundries. Thanks to the continuing stream of new electronic products striving for differentiation, we continue to witness the analog IC segment of the industry growing at a rate higher than the industry as a whole [Reference 1].
Fine-tuning key analog components
So what makes a high-precision analog chip design tick? Easy, it’s the combination of engineering talent and fine-tuning the key components. While skilled designers are very good at wringing maximum performance from a process, in the end they are limited by the sheer capability of the key components at their disposal.
Key analog CMOS components comprise MOS transistors, resistors, and capacitors. MOS devices are critical in every signal chain IC – amplifiers, ADCs, and DACs – while resistors are particularly important in DACs, and capacitors are the key to ADCs. Resistors and capacitors also play an important role in amplifiers, but they stand front and center in their respective converter applications.
For MOS transistors, typical parameters such as threshold voltage (VT) and drive current (ID,sat) are important – VT high enough to maintain low OFF-current (IOFF), while ID,sat is important since switches need low resistance and small footprint to minimize parasitic capacitances. However, critical new "care-abouts" for MOS devices come into play in the high-performance arena –1/f noise, substrate current (ISUB), overlap capacitance, and Early voltage (VA).
Noise is particularly important, since high-precision products often must maintain high signal-to-noise ratio (SNR) to pick a weak signal out of the background noise level. Noise must be measured early and often, and engineered, not simply recorded. Noise is often a ‘make or break’ parameter for high-precision chips.
Substrate current (ISUB) can be a real problem for high-precision designs. This effect is caused by hot-carrier collisions at the drain end of the channel, particularly for the NMOS device. ISUB can lead to total harmonic distortion (THD), so ISUB must be managed without significantly sacrificing IDsat. This requires additional efforts in drain engineering, well beyond the normal efforts to comply with device reliability requirements.
Parasitic capacitances in MOS transistors must be minimized wherever possible, as these can lead to SNR issues, since this capacitance creates voltage divider networks that can reduce the voltage across the intended capacitance. Even the metal system for a high-performance analog process must be scrutinized and optimized to reduce its parasitic effects.
MOS transistors are used as gain stages. Since gain is related to the output resistance (ro) of the transistor, this factor becomes important in high-performance designs. This is effectively the ‘flatness’ of the IV curves in the saturated region. This is sometimes called the Early voltage (VA), because it is a similar phenomenon exhibited by bipolar transistors where the term was coined. VA is a function of channel length and the drain engineering strategy. Higher VA, particularly for minimum devices, is desirable since the goal of the designer is to get the gain with minimum parasitic capacitance.
For resistors, the major considerations are sheet resistance and resistor tolerance as well as voltage and temperature coefficients. Simply stated, the designer wants an ideal device – a small footprint (to reduce parasitic capacitance), no variability with process, and no change in the value under any circumstance. This can be difficult with polysilicon (poly) resistors, which have well-known temperature characteristics and no simple way to trim their absolute value, and which also exhibit 1/f noise behavior [Reference 2].
As a result, a thin-film resistor (TFR) can be used instead due to its better overall behavior and capability to be laser-trimmed if needed. While the TFR is more difficult to process, requiring more masking steps, its added complexity can often mean the difference between a good product and a great product. For specialty, leading-edge products, this is often an easy decision.
For capacitors, the key concerns are capacitor density, tolerance, voltage coefficient, and dielectric absorption (DA), sometimes called hysteresis. This latter effect is a function of charge-trapping in the capacitor dielectric which can allow residual charge to reappear on the plates after discharging the component [Reference 3].
In many standard applications, designers want the highest capacitance/area they can get, but not necessarily so for high-precision analog. Here, the capacitor density is often reduced to minimize the total capacitance in the system since capacitor matching (discussed below) dictates larger sizes. Capacitor voltage coefficient is driven by the choice in capacitor-plate doping levels, while DA is governed by the choice in dielectric material, among other things. Clearly, a lot of characterization is required to understand these 2nd-order and 3rd-order effects in order to optimize the process.
For every component listed above, one parameter that is fundamentally important in analog design is component mismatch. Mismatch is defined as the percentage ratio of the difference between two identically designed components to their average value. Matching generally improves with larger component size (to a limit) [Reference 4]. The smaller the mismatch, the smaller the size of the components needed in the design which, in turn, leads to a smaller die and a lower die cost for a given design. This is a critical parameter that can used to weed out inferior processes.
For other product applications, specialty components may be needed such as junction field effect transistors (JFETs), for low-noise inputs, or drain-extended CMOS (DECMOS) devices for extended-voltage capability. These components require their own specialized optimization efforts and must be blended into the overall high-precision process in a manner that does not degrade the critical core components. These items will not be discussed here.
Now, all of this sounds very good indeed. However, the process developer’s job is not done when the wafers leave the wafer fab. It is critical to evaluate what comes afterwards. The performance gained in the wafer fab can easily be lost through the wafer thinning and IC packaging process steps due to stresses associated with the thinned wafer and packaging mold compounds.
Hence, careful attention must be paid to mitigating these deleterious effects. This can be done through the use of stress-relief layers, such as polyimide, or other such techniques, applied either at the end of the silicon process, prior to wafer thinning, or during the packaging process.
Accessing specialty analog CMOS processing from foundries
Electronic designers no longer need to rely exclusively on analog IDMs for high-performance analog CMOS performance to differentiate their products. Product manufacturers as well as fabless ventures can now gain early access to cutting edge analog CMOS processing through world class specialty foundries.
To gain insight into what a high-precision foundry process can deliver today, let us explore the attributes of the Dongbu HiTek’s HP180 process at the 0.18μm node. At the heart of this specialized analog CMOS process are finely tuned components. A comparison of 1/f noise for a typical logic CMOS process, a good, cost-effective analog CMOS process, and a high-precision analog CMOS foundry process (HP180) is shown in Figure 1a and Figure 1b, for both NMOS and PMOS devices.
Figure 1a and 1b. Noise comparison for digital, analog,
and high-performance analog CMOS devices:
a) NMOS and b) PMOS.
This specialized foundry process deploys a poly-poly approach, which allows a better selection of capacitor dielectrics to minimize DA while still achieving good voltage coefficients. By optimizing the doping of the poly plates, very low linear and quadratic terms can be achieved in single digits for both parameters. A representative plot of capacitor ratio vs. voltage is shon in Figure 2.
Figure 2. Capacitance vs. voltage for
high-performance poly-poly capacitor.
As shown in Figure 3, the HP180 thin-film resistor (TFR) specifies about 7 ppm/°C for a sheet resistance of 950 Ω/sq. In addition, the TFR matching performance is far superior to that of conventional poly resistors.
Figure 3. Relative comparison of matching performance for
polysilicon high-sheet resistor (HSR) and thin-film resistor (TFR),
both targeted at approximately 1KW/sq.
While many of the high-performance analog products envisioned by designers may be standalone types, the modularity of a specialty foundry process can enable dense logic (115K gates/mm2). This coupled with the ability to integrate non-volatile memory on-board further enables the high-performance process to easily migrate from standalone chips to SoCs.
Summary
High-performance electronic products demand high-precision analog CMOS process technologies that can implement near-ideal MOS transistors, resistors and capacitors as well as specialized JFET and DECMOS devices. To achieve differentiation in the final chip, such key components must be designed from the ground up, and precision engineered into the process throughout the entire development cycle. Once the exclusive domain of analog IDMs, such high-performance analog CMOS processing technologies are now accessible through specialty foundries. Thanks to this trend, designers can now achieve higher levels of differentiation faster by implementing their chip designs with foundry-developed analog CMOS processing.
References
1. ISuppli Report, Aug 2011.
2. S.L.Jang, "A model of I/f noise in polysilicon resistors", Solid-State Electronics, Vo1.33, No.9, pp.1155-1162, 1990.
3. J.W. Fattaruso, et al, “The effect of dielectric relaxation on charge-redistribution A/D converters”, IEEE Journal of Solid-State Circuits, v. 25, no. 6, Dec. 1990.
4. M. Pelgrom, et al, “Matching properties of MOS transistors”, IEEE Journal of Solid-State Circuits, vol. 24, no. 5, Oct 1989.
About the author
Lou N. Hutter is Senior VP and General Manager, Analog Foundry Business Unit, Dongbu HiTek. He holds 47 US patents and has authored numerous technical papers. Named a Texas Instruments Fellow in 1995, he earned his MSEE from MIT as well as BS degrees in math and physics from Northern Kentucky University. He can be reached at l.hutter@dongbu.com or +82-32-680-4140.
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