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Achieving high currents on PCBs with fine-pitch SMD components

Achieving high currents on PCBs with fine-pitch SMD components

Technology News |
By eeNews Europe



In switched-mode power supply systems or other circuits used in power electronics, the demand for control circuitry to use finepitch SMD components is ever increasing. At the same time, however, high currents of more than 100A will be present across the printed circuit board. Product developers face the challenge of finding a suitable yet financially viable solution.

In power electronic systems, the PCBs used often involve challenging technical requirements that force product developers to come up with particularly creative solutions to meet these requirements. Engineering compromises in key areas have to be made, since the sensitive control circuits normally have to use standard inexpensive SMD components. This calls for fine-pitch structures for the wiring and land pattern for the components, microcontroller and FPGAs.

Fine-pitch SMD structures are now easily achieved by the majority of PCB manufacturers for copper thicknesses in the signal layers up to 35µm – see figure 1. By way of contrast, to achieve the high currents needed for a MiniSKiiP module, i.e. to achieve 120 Amps in 35µm technology, either extremely wide wiring or copper surfaces would be needed to keep heat build-up at bay.


Fig. 1: Normal 35µm stackup design.

For such thicknesses, it would be virtually impossible for product designers to comply with clearance specifications if the PCB is to be small in size and, for cost reasons, the number of layers is to be kept to a minimum. The use of standard 35µm technology can therefore be ruled out here; instead, new solutions are required. Possible compromises might be to use thick copper or wirelaid technology.

Thick cooper stackup design

To achieve a satisfactory width for the individual high-current tracks, the stackup design has to be altered while the cross-sectional area of the conductor remains unaltered. If, instead of 35µm-thick copper, the layer thickness for the outer and inner layers is increased to 70µm and 105µm, respectively, suitable conductor widths can be achieved – see figure 2.


Fig. 2: PCB layout with 70 and 105µm thick copper.

Unfortunately, it is not possible to achieve fine pitches (clearances) on the 70µm-thick outer layers at a reasonable cost. Here, the ratio of circuit board conductor width to height would result in behaviour in production that is difficult to predict. An additional 35µm layer pair would resolve this problem technically; unfortunately, however, this would negatively impact the production costs.

Alternatively, in place of SMD components, traditional components with no fine-pitch clearances could be used and 70µm-thick copper used for the outer layers. This would normally result in a larger PCB. Another problem here is that some components are only available in fine-pitch technology, meaning that circuit redesign would be necessary.

Wirelaid technology as a compromise
A new technology available from a number of manufacturers such as Jumatech, Häusermann or others is wirelaid technology. Here, a wire with a rounded or rectangular cross-sectional area is integrated into the stackup design directly beneath the outer layer. In our circuit shown on figure 3, ribbon wiring with a 0.5mm-high and 4mm-wide cross-section is used.



Fig. 3: Wirelaid technology whereby a wire with a rounded or rectangular cross-sectional area is integrated into the stackup design directly beneath the outer layer.


In a micro-welding process, the copper wire is welded (or bonded) on the outer layer to form a positive-locking connection. The given outer FR4 dielectric layer is slightly thicker than usual and contains more resin, meaning that the wire is pressed into the FR4 layer. Using Allegro or OrCAD PCB Editor, a layer for the copper wire was defined directly below the top layer that describes the wire routing – see figure 4.



Fig. 4: A 35µm layout in wirelaid technology, shown in Allegro PCB Editor.


In the first internal signal layer, a Route Keep Out was defined below the wire. During the pressing process, the wire cannot form a short circuit with the signal wire on the internal layers. In the Cadence PCB Tool, the only settings to be made are those for the stackup design; plus, wirelaid technology can even be applied in the smallest scalable PCB design stage in OrCAD PCB design software.

Unlike the first solution using thick-film copper, the use of wirelaid technology does not impact the costs negatively. The additional costs for the wire are balanced out, for example by the savings made for the reduction in layer pairs and the use of standard copper thicknesses. An additional cost benefit is the reduced PCB dimensions as opposed to the dimensions achieved using thick copper technology.



Fig. 5: PCB 3D simulation using CAD data exported from Allegro & Nextra


To calculate the heatsink requirements, the PCB manufacturer using wirelaid technology has translated its experience into mathematical formulae. The calculation results were very close to the actual readings obtained in test measurements and a temperature difference of 20K was found compared to thick copper technology. A further advantage of wirelaid technology is that the surfaces are very planar and do not differ from standard PCBs built with 35µm technology.

PCB’s in wirelaid technology can conduct very high currents. This property is one of the core requirements for the use of PCB-based modules such as MiniSKiiP or SEMITOP (power modules produced by Semikron, where, for example, +DC, -DC and AC load connections are routed through the PCB). This technology uses far less space than conventional thick-copper PCBs.

Since circular and ribbon wires take up far less space on the PCB than special power layers, the number of layers can often be reduced. This technology can easily be designed with all of the individual design stages of the scaleable cadence PCB Design solution from OrCAD and Allegro.   

Peter Mauer is head of electronics design at Semikron Elektronik

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