Achronix branches out into FPGA IP with TSMC
While the company is branching out into FPGA fabric licensing it will continue to offer stand-alone FPGAs and Achronix is expected to offer a next-generation FPGA soon. But will they make use of Intel’s 14nm FinFET process or will Intel’s acquisition of Altera make a move to TSMC necessary?
But for now the focus is on Speedcore; essentially the core of the Speedster22i FPGAs – without the high-speed Serdes and I/O – available in different sizes to drop into system chips designed in TSMC’s 16FF+ FinFET process or Intel’s 14nm FinFET process. Achronix states that the Speedcore FPGA fabric will also be available for licensing and use in TSMC’s 7nm process in the first half of 2017.
The benefit of FPGA fabric compared with a separate FPGA. It is that signals don’t need to suffer the power consumption and latency of going off-chip. This can result with accommodating thousands of lines in and out of FPGA and approximately 10 times higher bandwidth, 10 times lower latency and 50 percent lower power. And by saving parts and printed circuit board space this can result in 90 percent lower cost Achronix said.
How Speedcore eFPGA eeduces power and cost compared with stand-alone FPGA. Source: Achronix.
FPGAs are inherently less efficient in area than fully diffused silicon but they bring the advantage of configurability and reconfigurability. About ten years ago stand-alone FPGAs have found a niche in compute and communications infrastructure and architectures based on multi-core CPUs and FPGAs have become conventional. Standalone FPGAs are convenient for low to medium volume applications but the ablility to integrate processor and FPGA fabric for hardware acceleration shows potential.
Next: Licensible FPGA fabrics
Licensible FPGA fabrics have been offered before without great success partly because of problems over design flow. But at the levels of integration now being offered it is perhaps an idea whose time has come. Achronix has at least one rival in this area (see FPGA cores offered for TSMC’s 40ULP process).
Speedcore has been designed in a modular fashion to support compilation and porting of the technology to different manufacturing processes and metal stacks.
Customers can then specify the die size, power consumption and resource configuration required for their application. Customers can also define the number of look-up-tables (LUTs), embedded memory blocks and DSP blocks, the aspect ratio, I/O port connections and can make tradeoffs between power and performance. Achronix delivers a GDS II of the Speedcore IP that customers integrate directly into their SoC, together with a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA.
Achronix uses standard IP business model, with an upfront license fee for access to the speedcore technology plus a royalty on device shipments containing Speedcore IP. In addition Achronix asks for maintenance fee to allow the ACE design tools to be kept up to date. Achronix expects an additional layer of functional IP to be offered to sit on top of its FPGA fabric but will support this provision by third parties by way of the creation of some sort of ecosystem club.
Speedcore has already been delivered to some customers under non-disclosure agreements and the company has achieved multiple design wins, said Steve Mensor, vice president of marketing at Achronix. “Typically those customers are asking for 50,000 to 150,000 LUTs,” he said. Tape-outs are expected by about mid-2017
Related links and articles:
News articles:
Intel samples Stratix 10 FPGAs on 14nm node
FPGA cores offered for TSMC’s 40ULP process
Achronix offers accelerator board for data centers
China’s Gowin expands non-volatile FPGA family
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