Adaptable platform eyes challenges of future computing

Adaptable platform eyes challenges of future computing

Technology News |
By Christoph Hammerschmidt

Designed to meet the computing demands of future automation landscapes in the areas of robotics, Internet of Things, automotive and many other fields of computing, including Artificial Intelligence, ACAP is a multi-core, heterogeneous platform that can be changed at the hardware level (even dynamically, during operation) to adapt to the needs of a wide range of applications and workloads. The company claims that ACAP delivers levels of performance and performance per-watt that is unmatched by CPUs or GPUs (see Interview with Xlinix CEO Victor Peng on the limitations of current computing architectures).

Future applications in the abovementioned areas have a number of challenges in store – to name a few of them are processing high amounts of data under tough real-time conditions, even stricter safety requirements along with the need to avoid delay times, video transcoding, data compression, AI inference, machine vision and network acceleration – and some of them combined at the same time. The ACAP platform is designed to meet these challenges, Xilinx promises. Now the company has announced the first product for the ACAP family. Baptized “Everest”, it will be manufactured in the latest semiconductor technology with structures as small as 7 nanometers. Tape-out is expected to take place later this year.

The development of the ACAP platform is part of a broader strategy intended to move Xilinx beyond FPGAs, explained CEO Victor Peng. Nevertheless, at the core of the ACAP platform one will find an FPGA fabric, albeit one that is utilizing distributed memory and hardware-programmable DSP blocks. In addition, the architecture contains multicore SoCs along with one or or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). An ACAP also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant (see image).

Dynamic reconfigurabilty and a broad
range of computing resources are
Xilinx’ answer to future computing challenges

To develop the whole platform, Xilinx spared no effort or expense: Four years of development time and an investment of more than one billion USD were necessary to devise the platform. The reward for potential customers, according to Peng: A 20-fold performance improvement for deep neural networks, compared to the company’s current Virtex VU9P FPGA.

More information:

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