Mediatek has used adaptive voltage control to achieve frequencies of 3.4GHz in the high performance ARMv9 x2 processor cores in a highly integrated 5nm 5G chip.
The fully integrated 5G chip has eight newly introduced ARMv9 cores with LPDDR5 memories and a 5G modem with AI, graphics and multimedia, built on TSMC’s 5nm process, says Ashish Nayak, principal engineer in the advanced CPU and technology division at Mediatek in Austin.
The SoC provides 5G cellular links for 3GPP Release 15 with data rates of 7Gbit/s down and 2Gbit/s up, as well as Wifi6e, Bluetooth 5.3 and GPS.
The heterogeneous CPU complex is organized into three ‘gears’. The first gear is a single HP core which uses the ARMv9 Cortex-X2 microarchitecture with 64KB L1 instruction cache, 64KB L1 data cache, and a 1MB private L2 cache.
The second gear consists of three Balanced Performance (BP) cores using the ARMv9 Cortex-A710 architecture, each with a 64KB L1 instruction cache, a 64KB L1 data cache, and a 512KB private L2 cache.
The third gear features four High Efficiency (HE) ARMv9 Cortex-A510 cores, with each core using a 64KB L1 instruction cache, 64KB L1 data cache. These HE CPU cores are implemented in pairs to facilitate the sharing of a 512KB L2 cache, floating-point and vector hardware between two CPUs cores, improving area and power efficiency, maintaining full v9 compatibility, without sacrificing performance of key workloads.
An 8MB L3 cache is shared across all the cores of the CPU complex. The HP core runs up to 3.4GHz clock speed to meet high-speed compute demands, while the HE cores are optimized to operate efficiently at ultra-low voltage. The BP cores provide a balance of power and performance for average workloads. Depending on the dynamic computing needs, workloads can be seamlessly switched and assigned across different gears of the CPU subsystem enabling maximum power efficiency.
Dynamic voltage and frequency scaling (DVFS) is employed along with adaptive voltage scaling to adjust operating voltage and frequency, achieving 27% improvement in single thread performance of the HP core over the BP core.
To further improve the power efficiency of the CPU subsystem, the design uses an adaptive voltage scaling (AVS) architecture by combining frequency-locked loop (FLL) and variation-resistant CPU speed binning technologies.
The FLL architecture addresses the challenge of limited power supply bandwidth, but is unable to cover for long-term (>ms) DC variations, such as supply load regulation or temperature variations. To achieve full-bandwidth protection and voltage margin reduction, a digitally controlled Ring Oscillator (ROSC) frequency-limiting mechanism is added to the FLL, to provide an operating condition reference. This is achieved by applying a minimum fine code (minFC) that the ROSC is allowed to operate on.
When the operating condition degrades, such as increased IR-drop, the FLL clock frequency will be limited to guarantee safe CPU operation. A voltage increase request, sent to the PMIC, is generated by comparing the FLL output frequency to the PLL input frequency. Conversely, when operating conditions improve and extra voltage margin is no longer needed, the ROSC will oscillate at PLL frequency with a fine code higher than minFC. A voltage decrease request will be sent to the PMIC to reduce the supply voltage until the FLL is frequency locked while using minFC for the ROSC.
Having taped out in May 2021, the voltage scaling in the chip was discussed in detail for the first time at ISSCC 2022 this week.
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