# ADC Guide Part 10: ADC Noise – 1

Analog-to-digital converters (ADCs) are one of the most commonly used blocks in embedded systems. Applications of ADCs include current sensing, motor control, temperature sensing and a myriad of others. As a consequence, understanding the basic specifications of an ADC and selecting an appropriate device for the given application is a must for reliable operation and cost-effective design.

This series of articles begins with the basics of ADCs, and then discusses different characteristics of an ADC that are important to design, including the impact of various irregularities, types of ADCs available on the market, advantages and disadvantages of each type, and how their selection varies from application to application.

In Part 10 and 11, we tackle noise issues.

Noise is one of the most important AC specifications of an ADC. It can drastically change overall system response. To meet system requirements, engineers need to understand the noise performance of all the analog peripherals in the signal chain, including the ADC. There are various noise components that add to overall ADC noise. Further complicating noise is that these components may be defined differently in ADC datasheets. In this part of the article series, we will talk about the effect of noise on an ADC’s output.

The very process of analog-to-digital conversion generates noise. As we saw in the first part of this article series, for an ideal ADC, this noise is limited to quantization noise. However, there are a number of noise sources present in a practical ADC apart from just the quantization noise. Thermal noise, 1/f noise, clock jitter, etc. are also sources of noise in ADC. Note that out of the various factors that separate a practical ADC from an ideal ADC, nonlinearity is not considered as part of ADC noise since it is accounted for as distortion in the output of the ADC.

**Figure 1: FFT of output of an ADC**

The collective effect of these noise sources on an ADC can be seen in the ADC characteristics as code transition noise. As the name suggests, code transition noise refers to the uncertainty in the analog input voltage at which the ADC output code makes its transition. **Figure 2 **shows the transfer characteristics of a 3-bit ADC with the effect of code transition noise considered. Transitions are most probable at the most dense region of the range of transition voltages. For a neatly designed ADC, this would coincide with the transition point of ideal ADC characteristics.

**Figure 2: Effect of code transition noise in ADC transfer characteristics**

As said earlier, the FFT output gives a fair idea about the power of noise present in the output of an ADC. Noise is present at all other frequency contents apart from the fundamental signal frequency and the harmonics of the fundamental frequency. We can compute the noise power in the ADC output by adding the power of individual noise frequencies. Conventionally, the RMS value of all the frequencies is termed as the noise voltage in the output of an ADC. In **Figure 1**, *v*_{noise} represents such an RMS noise level. It can be computed as:

**Click on image to enlarge.**

The symbol *v* inside the summation sign represents the individual voltage levels of every noise frequency (i.e., all frequency components except for the signal and harmonic frequencies).

The noise voltage as defined above is useful for the purpose of computing some of the ADC’s AC parameters such as signal-to-noise ratio (SNR). However, it fails to give a clear picture of how much the output of an ADC can fluctuate when a certain voltage is given at the input of ADC. To understand this, another test procedure is employed. The input of the ADC under test is grounded and a number of output samples are collected. A histogram is plotted with the output code on the x axis and the number of occurrences on the y axis. This histogram is popularly referred to as a grounded-input histogram since the input is nominally at zero volts. This histogram serves as a very important tool in calculating various noise parameters related to the ADC. It should be noted that this test gives the noise performance of just the ADC. Since the input is constant DC, ADC nonlinearities and AC noise sources such as noise due to jitter in the sampling clock do not come into picture.

**Measuring noise**

This method of measurement of noise in an ADC is fairly simple and can even be easily implemented on a system level after the ADC is placed in the final system on a PCB. As stated above, we would need to ground the analog input terminals of the ADC and take a number of readings to plot the histogram. We will now see, with the help of the sample histogram in **Figure 3**, how to calculate the noise parameters of an ADC.

**Figure 3: Grounded input histogram of an ADC**

**Figure 3 **depicts a typical grounded input histogram of an ADC. We can define a number of parameters in terms of counts of ADC output with the help of this histogram. For example, the peak-to-peak noise of an ADC is the span of x axis over which the grounded input histogram exists. For example, the peak-to-peak noise for the ADC corresponding to **Figure 3** is (1 – (-3)) or 4 counts. Alternatively, it can be expressed in number of LSBs of ADC output. In the aforementioned case, peak-to-peak noise would be (log_{2} 4) = 2 LSBs.

In the next installment of this series (**ADC Guide Part 11**), we will continue talking about the noise performance, EnoB, and SINAD specifications of an ADC.

**Earlier articles** are listed below:

- Part 1: the ideal analog/digital converter
- Part 2: the sampling rate
- Part 3: offset error
- Part 4: gain error and gain error drift
- Part 5: ADC non-linearity (DNL/INL) and monotonic transfer function
- Part 6: Common mode input, CMRR, and PSRR
- Part 7: ADC reference basics, pt.1
- Part 8: ADC reference basics, pt.2

**About the authors**

**Sachin Gupta** is working as Product Marketing Engineer 2 with Cypress Semiconductor. He holds a Bachelor’s degree in Electronics and Communications from Guru Gobind Singh Indraprastha University, Delhi. He has several years of experience in mixed signal application development. He can be reached at sgup@cypress.com.

**Akshay Phatak** is an Applications Engineer with Cypress Semiconductor. He holds a Bachelor’s degree in Electronics and Telecommunications form College of Engineering, Pune (India). He likes to work on mixed-signal embedded systems. He can be reached at akay@cypress.com.