Advances within the JESD204B converter protocol
The JESD204 standard applies to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). It is primarily intended to provide a common interface to FPGAs, but may also be used with ASICs designs.
As the resolution and speed of converters has increased, the demand for a more efficient interface has grown. The JESD204 interface brings this efficiency and offers several advantages over its CMOS and LVDS predecessors in terms of speed and size. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes that make board designs much easier.
The JESD204 standard is also easily scalable so it can be adapted to meet future needs. This has already been exhibited by revisions the standard has undergone. In fact, the JESD204 standard has seen two revisions since its introduction in 2006 and is now at revision B. As the standard has been adopted by an increasing number of converter vendors and users, as well as FPGA manufacturers, it has been refined, and new features have been added that have increased efficiency and ease of implementation.
What is JESD204B?
The original version of JESD204 was released in April 2006. The standard describes a multi-gigabit serial data link between converter(s) and the device(s) to which they are connected — typically devices such as FPGAs or ASICs. In the first version of JESD204, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver. The lane is the physical interface between M number of converters and the receiver, which consists of a differential pair of interconnect utilizing current mode logic (CML) drivers and receivers. The link is the serialized data link that is established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.
Although both the original JESD204 standard and the revised JESD204A standard were higher performance than legacy interfaces, they were still lacking a key element. This missing element was deterministic latency in the serialized data on the link. When dealing with a converter, it is important to know the timing relationship between the sampled signal and its digital representation in order to properly recreate the sampled signal in the analog domain once the signal has been received (this situation is, of course for an ADC, a similar situation is true for a DAC). This timing relationship is affected by the latency of the converter, which is defined for an ADC as the number of clock cycles between the instant of the sampling edge of the input signal until the time that its digital representation is present at the converter’s outputs. Similarly, in a DAC, the latency is defined as the number of clock cycles between the time the digital signal is clocked into the DAC until the analog output begins changing.
In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the converter and its serialized digital inputs/outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.
In July 2011, the second and current revision of the standard, JESD204B, was released. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the data rates supported were pushed up to 12.5 Gbit/s, broken down into different speed grades of devices. This revision of the standard calls for the transition from using the frame clock as the main clock source to using the device clock as the main clock source. The illustration below provides a high-level representation of a JESD204B system that highlights the additional capabilities added by the JESD204B revision.
High-level representation of a JESD204B system.
In the previous two versions of the JESD204 standard, there were no provisions defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link re-synchronization events, the latency should be repeatable and deterministic. One way this is accomplished is by initiating the initial lane alignment sequence in the converter(s) simultaneously across all lanes at a well defined moment in time by using an input signal called SYNC~.
Another implementation is to use the SYSREF signal, which is a newly defined signal for JESD204B. The SYSREF signal acts as the master timing reference and aligns all the internal dividers from device clocks as well as the local multi-frame clocks in each transmitter and receiver. This helps to ensure deterministic latency through the system. The JESD204B specification calls out three device sub-classes: Sub-class 0 (no support for deterministic latency), Sub-class 1 (deterministic latency using SYSREF), and Sub-class 2 (deterministic latency using SYNC~). Sub-class 0 can simply be compared to a JESD204A link. Sub-class 1 is primarily intended for converters operating at or above 500 MSPS, but it can be used on converters operating below 500 MSPS to achieve greater timing resolution. Sub-class 2 is primarily for converters operating below 500 MSPS.
In addition to the deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gbit/s and divides devices into three different speed grades. The source and load impedance is the same for all three speed grades being defined as 100Ω ±20%. The first speed grade in JESD204B aligns with the lane data rates from the JESD204 and JESD204A versions of the standard and defines the electrical interface for lane data rates up to 3.125 Gbit/s. The second speed grade defines the electrical interface for lane data rates up to 6.375 Gbit/s. This speed grade lowers the minimum differential voltage level to 400 mV peak-to-peak, down from 500 mV peak-to-peak for the first speed grade. The third speed grade defines the electrical interface for lane data rates up to 12.5 Gbit/s. This speed grade lowers the minimum differential voltage level required for the electrical interface to 360 mV peak-to-peak. As the lane data rates increase for the speed grades, the minimum required differential voltage level is reduced to make physical implementation easier by reducing required slew rates in the drivers.
To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were the same. This did not offer a lot of flexibility and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives its respective device clock from a clock generator circuit, which is responsible for generating all device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.
Space savings
The number of pins required for the same given converter resolution and sample rate is also considerably less. The table shown below provides an illustration of the pin counts for the three different interfaces using a 250 MSPS converter with various channel counts and bit resolutions. The data assumes a synchronization clock for each channel’s data in the case of the CMOS and LVDS outputs, and a maximum data rate of 5.0 Gbit/s for JESD204B data transfer using the CML outputs. Even with a limitation imposed on the JESD204B lane rate, the number of pins required is much less for the case of the JESD204B implementation. The motivation for the progression to JESD204B using CML drivers is quite obvious when looking at this table and observing the dramatic reduction in pin count that can be achieved.
Pin count comparison for a 250 MSPS, 14-bit ADC.
To help further illustrate the advantages of moving from LVDS to JESD204B, the image below shows the reduction in layout complexity for the JESD204B outputs. The example shows two 14-bit, dual-channel, 250 MSPS ADCs — the AD9643 and the AD9250. In the case of the AD9643 (left) there are 30 output lines routed for the digital outputs (one synchronization clock is sent for both channels in this case). By comparison, in the case of the AD9250 (right) there are four output lines routed for the digital outputs.
Comparison of dual 14-bit 250 MSPS ADC layout: LVDS (left) versus JESD204B (right).
As can be seen, the LVDS lines on the AD9643 evaluation board must be carefully routed such that all the lengths are carefully matched to avoid timing issues in the FPGA where the data is received. This makes the output routing more complex and tedious. However, in the case of the AD9250 evaluation board, the output lines for the JESD204B CML outputs are quite simple to route since there are only four to be concerned with. This helps further illustrate the advantages of moving to JESD204B.
JESD204B device configuration flexibility
Although converters may have JESD204B serial lanes defined by a number, letter, or other nomenclature to designate their particular relevance in the complete link, they are not required to be fixed. The specification allows for re-mapping of these assignments in the initial configuration data, as long as each lane and device has a unique identification. The link configuration data includes the device and lane identification numbers to identify its operation. With this information, a multiple-lane transmitter could easily reassign any digital, logical, serial data to any physical output lane using a cross-bar mux.
While it is an optional feature that the specifications allow, if an ADC vendor has a cross-bar mux feature to reassign logical to physical output assignments, then the link I/O can be reconfigured in the best order for the easiest layout. The FPGA receiver can take the same initial configuration data and change the expected lane assignments to recover the data. With this ability, the routing of lanes from one device to the other can be made much easier and independent of the initial named assignment by the silicon vendor in the datasheet.
The differential impedance of each trace pair should be 100Ω, with a termination of 100Ω at the receiver. It’s also important not to neglect impedance discontinuities at interconnects and to maintain a near 100Ω differential transmission line over connectors. In general, system layout should aim to minimize signal loss on the JESD204B link and adhere to the interconnect insertion loss mask in the specification for the particular application baud rate. Also, an AC-coupled approach is suggested to mitigate mismatches in common-mode voltages at the transmit and receive devices.
While the physical layer (PHY) is characterized at the component pin level by the converter and FPGA providers, what design engineers really want to know is how well the PHY layer works in their particular system. A new FPGA software eye scan tool called Analog Devices Linux JESD204B Eyescan software – that was developed by Analog Devices and Xilinx – is now available to identify that detail. The JESD204B receiver can provide additional adaptive gain control (AGC) and equalization (EQ) to amplify the high-frequency component of the far-end signal. An improved 2D data eye can therefore be seen internally after these circuit blocks, as compared to the input pin ahead of these circuits. By accurately sweeping a comparator voltage against small time delays, a complete recovered eye scan of the signal after these blocks can be realized. This provides an internal electrical probe point to the signal that the JESD204B receiver inside the FPGA actually uses to processes the serial bit stream.
JESD204B physical layer evaluation.
Each JESD204B differential lane should be matched in length intra-pair between the +/- signals. While lane-to-lane, or inter-pair, length matching is not critical, matched lengths within a pair are still important. Any intra-pair trace mismatch will close down the available data eye seen at the receiver, effectively limiting the bandwidth of the link.
The JESD204B PHY of an ADC or DAC can be modeled using what is known as an IBIS-AMI (I/O Buffer Information Specification-Algorithmic Modeling Interface) model. IBIS-AMI not only provides the I/O characteristics of the pin, it also offers a way to simulate the behavioral algorithm of the PHY layer. With this capability, system designers can measure the impact of jitter, rise/fall times, pre-emphasis, and equalization within the signal path of their systems.
This type of model provides several advantages for system designers. It’s interoperable with many advanced simulation packages, so models from different semiconductor vendors can be run together to simulate both ends of a link. Users can set the silicon control parameters in the IBIS-AMI model as needed for their system and even simulate a matrix of options to find the best-case profile. And with the model’s efficient performance, multimillion-point simulations can be run in a matter of minutes.
JESD204B calls for some mandatory test patterns to be made available on the link by the transmitter. These patterns are necessary to be able to validate the data integrity of the serial interface. One set of patterns sends a continuous sequence of pre-determined control characters that will allow the testing of jitter, code group synchronization, and a receiver eye mask. Another pattern sends a repeated initial lane alignment sequence request to the receiver. A final set contains pseudorandom and pre-determined data with varying lengths of repetition. These patterns can be used to test the bit error rate (BER) on the link, as both the transmitter and receiver know the expected sequence of data. When the patterns are used in conjunction with the eye scan tool, a complete BER of the link can be measured.
Conclusion
As the speed and resolution of converters have increased, the demand for a more efficient digital interface has increased. The industry began to address this with the JESD204 serialized data interface. The interface specification has continued to evolve to offer a better and faster way to transmit data between converters and FPGAs (or ASICs).
Looking to the future of converter digital interfaces, it is clear that JESD204 is poised to become the industry choice for the digital interface to converters. Each revision has answered the demands for improvements on its implementation and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performance pushes higher, the JESD204 standard should be able to adapt and evolve to continue to meet the new design requirements necessary.
There are many advantages that JESD204 brings to the table. Designers need not fear new and expensive tools. With the creation of low-cost development tools, such as the Analog Devices Linux JESD204B Eyescan software, system design implementation can be realized with a low burden rate on the engineering team. Using tools such as these, along with the modeling capabilities provided by the IBIS-AMI models, designers can easily migrate to this new interface without a large expense in time or cost. State-of-the-art systems with high sample rate converters can be designed without overly burdening system designers with expensive analysis equipment.
This article first appeared on the EE Times website.
Related links and articles:
News articles:
Critical issues for a functioning JESD204B interface
Xilinx, Analog achieve JESD204B interoperability
An overview of the JESD204 standard for ADCs
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