Agile Analog aims for complete analog sub-system IP
Agile Analog has launched its first range of analog blocks packaged to look like digital IP blocks. This is the first step to a fully configurable analog subsystem generated by its Composa tool with the required verification models later this year.
The initial sub-system blocks cover power management, PVT sensing and sleep management and are digitally wrapped to significantly reduce the integration effort.
The digital wrappers provide standard interfaces such as the AMBA APB bus to ease integration. This is especially of interest to digital RISC-V chip developers, Chris Morrison, director of product marketing at Agile tells eeNews Europe.
“We are starting with power management, sleep management and PVT sensors , but we will have new ones in the next 12 months such as sensor interface, ADCs and DACs to help with BIST, more advanced PVT sensors and power management units. Then a full analog subsystem, that’s not far away,” he said.
“We designed this for two reasons – particularly around RISC-V we saw people trying to integrate analog for the first time and we can make their life much, much easier by doing this,” he said. “But we also found that customers for example want a low drop out (LDO) regulator but actually need a power management unit. So most of our sales are not individual IPs but blocks and we optimise the IPs, formalise these and wrap the digital around it.”
The key is the verification that is included as well. “We give a System Verilog model for a digital verification environment,” said Morrison. “We are making it look digital to the verification engineer.”
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“We will handle all the verification, we verify all the analog ourselves, and the analog and digital interfaces, then all the engineer is left with is to integrate and verify the IP like they would a digital block,” said Morrison.
“For example there are there are metastability issues that need dealing with in mixed signal verification such as clock domain crossings and these kind of issues we think we can fix. As we provide the digital interface it only needs to be a digital representation as the analog is covered in our mixed signal verification,” he said.
“The customer is welcome to use the analog verification but we provide the SystemVerilog models and the actual RTL to interface to the analog as that is how we hide the issues that the engineers has to deal with. We fix any analog and mixed-signal verification issues that come up so they are resolved before the customer gets our IP.”
This will lead to a full analog sub-system that can be generated by the company’s Composa tool
“Traditionally when integrating multiple blocks of analog IP there is sandbagging that needs to go on to ensure interoperability such as the size of the output drivers. But once you put in a subsystem you know where everything is, the drivers can be the right size, the drivers can be smaller, lower power, the noisy parts can be at one end,” he said.
The wide range of RISC-V chip designs is also an advantage, he says.
“As an IP company fragmentation is good for us,” he said. “Because we offer customisation to all our customers we need to bake in verification into our Composa tool and that’s the reason the subsystems works for us. All the interfaces are defined up front and we work down to the transistors.”
Analog IP sub-system blocks
The agilePMU Subsystem is an efficient and highly integrated power management for SoCs/ASICs with power-on-reset, multiple low drop-out regulators, and an associated reference generator. It also includes an integrated digital controller for precise control over start-up and shutdown, supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem
The agilePVT Sensor Subsystem is a low power integrated macro consisting of process, voltage, and temperature sensors, and an associated reference generator, for on-chip monitoring of a devices’ physical, environmental, and electrical characteristics. This also has an integrated digital controller the agilePVT Subsystem offers precise control over start-up and shutdown. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.
The agileSMU Subsystem provides the IP blocks required to securely manage waking up a SoC from sleep mode. This typically has a programmable oscillator for low frequency SoC operation and RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC. The integrated digital controller the agileSMU Subsystem offers precise control over wake-up commands and sequencing. Status monitors provide real-time feedback on the current state of the subsystem.
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