Agile Analog launches first complete RISC-V analog IP subsystem

Agile Analog launches first complete RISC-V analog IP subsystem

New Products |
By Nick Flaherty

Agile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips.

The initial subsystem includes all the analog IP required for a typical battery powered IoT system. These include the power management unit (PMU), a sleep management unit (SMU), and data converters detailed by eeNews Europe in April. The process agnostic, customisable and digitally wrapped analog IP subsystem will pair with a RISC-V core to form a complete design for digital chip developers.

“The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP solutions is increasing. One of the major challenges that digital chip designers face is in integrating the analog circuitry to support their SoC designs,” said Chris Morrison, Director of Product Marketing at Agile Analog.

“With our RISC-V analog IP subsystem, it’s possible to access the appropriate analog IP for a specific process and foundry. This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications. As with all of the Agile Analog IP, this subsystem is customizable to give the exact feature set required for the application.”

Traditional analog IP has been a major bottleneck for many years, with limited options available, and chip designers have struggled to integrate multiple analog IP blocks, often from multiple vendors. The design and verification of the mixed-signal boundary between analog and digital in particular is a challenge. The digitally wrapped approach with fully verified IP addresses this as the complete subsystem is verified in both analog and digital environments, connects directly to the MCU’s peripheral bus, and is supplied with a SystemVerilog model for easy integration into an SoC’s existing digital verification environment. 

Agile Analog will be exhibiting and presenting at the RISC-V Summit Europe 2023 this week in Barcelona.


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