Low power memory developer SureCore is working with Agile Analog in Cambridge on IP for chips for quantum computing sampling next year.
Agile is developing power management and analog blocks for chips that operate in cryogenic temperatures as the interface to quantum processors using its Composa tool. A test chip is under development for tapeout early next year with low temperature memories from SureCore.
This follows the development of a cryogenic process development kit (PDK) for the GlobalFoundries 22FDX FD-SOI process developed by Semiwise in Scotland in the CryoCMOS project.
“The aim of the project was focussed on foundation digital IP and this is a key milestone with a test chip with recharacterized standard cell libraries so that anyone can theoretically design a control chip,” Paul Wells, CEO fo SureCore tells eeNews Europe. “But quite a lot of analog circuitry is needed and the DACs monitor high frequency circuitry as well so its about getting a range of IP availability.”
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“The aim of the project is to provide quantum computing companies with a portfolio of IP that is working at the cryogenic temperatures so they can user a standard foundry with GF 22FDX,” said Wells. “We plan for this to be the start of more collaboration with Agile on taking the technology forward.”
“The reason we worked with SureCore on the project was to explore whether we could use the PDK to see how if it works,” said Chris Morrison, director of product development at Agile Analog. “With Composa one of the things we can show across automotive and military temperature ranges is we can take in the PDK and generate the cores.”
“The quantum computing space is very fragmented and they need IP and memory and data converters and power management which we offer,” he said. “Most need five DACs per qbit and that becomes a lot of DACs very quickly when you scale to thousands or hundreds of thousands of qubits and the costs quickly become astronomical.”
“We are shooting for a February tapeout with samples in the summer and we will be evaluating those,” said Wells at SureCore.
Agile has also developed sub-systems with data conversion and power management.
“A big focus for us is the data converter space and that’s where I see us adding value here. At this stage I don’t see us doing a big sub-system. We would work with customers for them to do that themselves,” said Morrison.
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“It needs to be low power, it needs to be fast,” said Morrison. “We are already engaged with a couple of these companies, people are happy with 100 to 500Msample speeds and at that sped the power is reasonable. We can be very competitive with power with conventional designs.
“Our tool works in the same way as an analog engineer would design a solution so we can optimise for power or performance in the same way. We might have to hand optimise but it will be small tweaks rather than huge optimisations,” said Morrison.
“Whenever we onboard a PDK we have an automated process to verify it and make sure the power is as low as possible and this allows our engineers to play with the PDK to work out the optimisations for analog and we are in discussion s on whether there are other companies we should work with for an combined devices.”