Agilent explains SSIC, CSI-3 interface needs: plans analyser release
Mobile designers are adding multiple high-speed buses to their designs to manage multiple high-resolution cameras, advanced graphics adapters and on-board memory. These high-speed buses contribute to increasing demand for bandwidth, which has driven the expansion of the M-PHY specification to include four-lane, 6.0-Gbps options. The U4431A offers up to 16 GB of analysis memory on each lane, allowing designers to capture tens of seconds of system traffic, even at these high speeds.
The instrument has a raw data mode, a feature that lets designers see the time-correlated 8b/10b data that underlies each protocol. Designers can view the data in a waveform or listing format, providing insight into how a packet is formed at the physical layer. The visibility extends throughout the M-PHY protocol stack, allowing error detection from the physical layer to the link and from the transport layers to the high-level application layer.
The instrument comes in modular AXIe blade form; you can analyse multiple M-PHY buses simultaneously. These M-PHY buses can be time-correlated with MIPI D-PHY CSI-2 and DSI-1, PCIe, DDR and HDMI buses—or even generic high-speed logic analyser modules. Designers can purchase as many lanes and as much memory and protocol support as they need.
“The M-PHY is critical to the implementation of next-generation mobile computing products, including smartphones, tablets and laptops,” said Joel Huloux, chairman of the board of MIPI Alliance.
Agilent also announced preliminary support for Mobile PCI Express (M-PCIe) with availability to all customers to be announced in the second quarter of 2014. M-PCIe maps the broadly adopted PCIe standard to the M-PHY physical layer, and it will be first seen in memory applications. The MIPI M-PHY protocol analyser will be delivered in September 2014.
Agilent; www.agilent.com/find/mphy_analyzer
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