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Agilent Technologies launches latest version of its RFIC simulation software

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Updates for RF design analysis include carrier-analysis improvements that deliver significantly better scalability and performance on multicore CPUs, improved performance of carrier and SSNA noise analyses, fast yield-contributor analyses for RF and analog/mixed-signal designers, including DC, AC and oscillator analysis, and enhanced fast circuit-envelope analysis that accelerates RF functional path simulations by an order of magnitude or more.

The software offers broader support for RFIC-centric source configurations for models including memory effects, it provides an enhanced crystal oscillator convergence option that reduces the frustration of simulating crystal oscillators. GoldenGate version 2011 boasts a number of improvements for wireless design verification. Fast mismatch analysis dramatically accelerates the block and functional path verification that RFIC designers perform every day, without loss of accuracy, including new support for Cadence corners tool.

The updated adslib for the GoldenGate library now includes delay-defined transmission lines and Philips-TU Delft standard/user-defined bondwire models. Using this, engineers can simulate more of their designs by including RF package and board effects. Additionally, by closing the loop between system and circuit designers using the new SystemVue and GoldenGate links and flows, designers can greatly accelerate system-level verification of RFICs.

More information on GoldenGate version 2011 at www.agilent.com/find/eesof-goldengate2011

Visit Agilent EEsof EDA Software at www.agilent.com/find/eesof


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