AHB cache controller IP improves performance of NVM in SoCs
R-Stratus-LP provides advanced NVM based devices architecture with significant gains:
- Power consumption of embedded or external NVM can be divided by as much as a factor of three
- Apparent frequency is accelerated by the same factor
R-Stratus-LP is claimed to be the first L1 cache controller with an architecture optimised for low-power; the architecture is designed to minimise the number of accesses to TAG and cache RAM and NVM memory. Cache line size and associativity are both runtime programmable, on the fly.
This cache controller has also been designed for implementation by SoC integrators; support of AHB-Lite interfaces ensures easy integration within any MCU subsystem without need for any bridge function. TAG and cache RAM memories are kept separate from R-Stratus logic in order to ease portability across a wide range of process technologies.
Dolphin Integration; www.dolphin.fr/flip/logic/peripherals/logic_stratus.html
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