AI ASIC design IP platform now available
The neuASIC platform, says the company, removes the restrictions faced by static ASIC designs caused by changing AI algorithms that are difficult for such designs to adapt to. Featuring a customized, targeted IP offered in 7-nm FinFET technology and a modular design methodology, the platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators.
“Our goal with the neuASIC platform was to allow faster, more energy efficient AI ASIC design that was adaptable to changing algorithm requirements,” says Patrick Soheili, vice president, business and corporate development at eSilicon. “I am confident the current IP platform will achieve this goal. Our extensive custom memory design capability has been a key enabler to deliver the required functionality.”
The platform includes the following compiled, hardened and verified functions:
- Configurable multiply-accumulate (MAC) blocks
- Single-port SRAM
- Pseudo two-port and pseudo four-port SRAM
- Ternary content-addressable memory (TCAM)
- Pitch match memory
- GIGA memory
- WAZPS (word all zero power saving) memory
- Transpose memory
- Re-mapper – low power cross-bar
- Convolution engine
- 56G SerDes
- HBM2 PHY
The platform also provides a software AI accelerator builder function that provides power/performance/area estimates of the chosen ASIC architecture before register-transfer level (RTL) development starts.
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