AI optimisation moves into system design tools
Cadence Design Systems has launched an AI-driven optimisation tool for system design that can speed up development by a factor of 10.
The Optimality Intelligent System Explorer enables multi-disciplinary analysis and optimization (MDAO) of electronic systems, and can accelerate designs by as much as 100x, says Cadence.
Optimality uses similar AI technology to the Cerebrus Intelligent Chip Explorer and initially works with the Cadence Clarity 3D Solver for 3D electromagnetic (EM) analysis and Sigrity X technologies for high-speed signal integrity (SI) and power integrity (PI) analyses.
The AI-driven tool allows design teams to explore the entire design space and quickly and efficiently converge on the optimal design. This can help teams avoid suboptimal local minima and maxima, while mapping variations for additional consideration and exploration of the complete design space.
A flexible user interface allows customers to activate Optimality Explorer from the Clarity and Sigrity X environments.
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MediaTek is using the tool for its high speed serial/deserialiser (SerDes) designs where signal integrity is a key design factor and the Sigrity X tool support analysis of signals up to 112GHz.
“The Cadence Optimality Explorer and Clarity 3D Solver allowed us to realize a 75% performance improvement for our recent 112G PAM4 SerDes project,” said Aaron Yang and Howard Yin, Design Directors at MediaTek. “The optimum return and insertion loss, and TDR waveforms, were determined quickly and efficiently due to Cadence’s breakthrough AI-driven optimization, accelerating the design team’s productivity and ultimately the success of the final product.”
It also being used for AI chip designs at Baidu and Ambarella.
“The Clarity 3D Solver provided unparalleled speed and capacity with proven accuracy throughout our next-generation Kunlunxin AI chip project,” said Canghai Gu, Chief Chip Architect of Kunlunxin at Chinese AI giant Baidu.
“ We utilize Clarity 3D Solver for high-speed channel modeling and optimization. Now, with Cadence’s Optimality Explorer, we reduced the amount of time we spent on optimizing transmission line performance from hours to minutes,” he said. “We were able to tune the physical parameters of a high-speed differential pair routing constraint much faster than previous methodologies. The time saved can be used to optimize other parts of our design so that all critical interfaces operate at peak performance.”
“In a high-speed package design, it’s a cost- and performance-effective process to optimize the design before taping out. For our DDR package optimization process, Cadence’s Optimality Explorer-empowered Clarity 3D Solver enabled us to uncover the best parameter configuration, meeting our design criteria in a dramatically shorter time window, thereby speeding up our time to market while enabling us to deliver a higher performing solution,” said Alan Zhu, VP of Hardware at US AI chip designer Ambarella.
Microsoft used the tool for PCB designs. “As an early adopter of the Cadence Optimality Intelligent System Explorer, we stressed its performance on a rigid-flex PCB with multiple via structures and transmission lines. The Optimality Explorer’s AI-driven optimization allowed us to uncover novel designs and methodologies that we would not have achieved otherwise. Optimality Explorer adds intelligence to the powerful Clarity 3D Solver, letting us meet our performance target with accelerated efficiency,” said Kyle Chen, Principal Hardware Engineer at Microsoft.
“For years, optimization at the system level has been extremely inefficient based on a human-intensive workflow of design/prototype/test/refine and eventual manufacturing,” said Ben Gu, vice president of R&D for the Multiphysics System Analysis Business Unit at Cadence. “With Optimality Explorer’s MDAO capability, it’s now possible to perform system-level optimization, from the IC to the package, the PCB and the system, in a fraction of the time.”
The Optimality Intelligent System Explorer is available now to select customers through early access. General availability is expected in the fourth quarter of 2022.
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- Faster timing closure of high-speed PCB interfaces
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